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| 1 features ? avr ? ? high-performance and low-power risc architecture ? 118 powerful instructions ? most single clock cycle execution ? 32 x 8 general-purpose working registers ? up to 8 mips throughput at 8 mhz data and nonvolatile program memories ? 8k bytes of in-system programmable flash spi serial interface for in-system programming endurance: 1,000 write/erase cycles ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 512 bytes internal sram ? programming lock for software security peripheral features ? 8-channel, 10-bit adc ? programmable uart ? master/slave spi serial interface ? two 8-bit timer/counters with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare and capture modes and dual 8-, 9-, or 10-bit pwm ? programmable watchdog timer with on-chip oscillator ? on-chip analog comparator special microcontroller features ? power-on reset circuit ? real-time clock (rtc) with separate oscillator and counter mode ? external and internal interrupt sources ? three sleep modes: idle, power save and power-down power consumption at 4 mhz, 3v, 20 c ? active: 6.4 ma ? idle mode: 1.9 ma ? power-down mode: <1 a i/o and packages ? 32 programmable i/o lines ? 40-lead pdip, 44-lead plcc, 44-lead tqfp, and 44-pad mlf operating voltages ?v cc : 4.0 - 6.0v at90s8535 ?v cc : 2.7 - 6.0v at90ls8535 speed grades: ? 0 - 8 mhz for the at90s8535 ? 0 - 4 mhz for the at90ls8535 8-bit microcontroller with 8k bytes in-system programmable flash at90s8535 at90ls8535 rev. 1041h?11/01
2 at90s/ls8535 1041h?11/01 pin configurations 3 at90s/ls8535 1041h?11/01 description the at90s8535 is a low-power cmos 8-bit microcontroller based on the avr risc architecture. by executing powerful instructions in a single clock cycle, the at90s8535 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. block diagram figure 1. the at90s8535 block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porta data dir. reg. portd data dir. reg. portc data register portb data register porta analog mux adc data register portd data register portc programming logic timing and control oscillator oscillator interrupt unit eeprom spi uart status register z y x alu portb drivers porta drivers portd drivers portc drivers pb0 - pb7 pa0 - pa7 reset vcc avcc agnd aref gnd xtal2 xtal1 control lines + - analog comp ara tor pd0 - pd7 pc0 - pc7 8-bit data bus 4 at90s/ls8535 1041h ? 11/01 the avr core combines a rich instruction set with 32 general-purpose working regis- ters. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the at90s8535 provides the following features: 8k bytes of in-system programmable flash, 512 bytes eeprom, 512 bytes sram, 32 general-purpose i/o lines, 32 general- purpose working registers, real-time clock (rtc), three flexible timer/counters with compare modes, internal and external interrupts, a programmable serial uart, 8-chan- nel, 10-bit adc, programmable watchdog timer with internal oscillator, an spi serial port and three software-selectable power-saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscilla- tor, disabling all other chip functions until the next interrupt or hardware reset. in power save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the device is manufactured using atmel ? s high-density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface or by a conventional nonvolatile memory programmer. by combining an 8-bit risc cpu with in-system programmable flash on a monolithic chip, the atmel at90s8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the at90s8535 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits. pin descriptions vcc digital supply voltage. gnd digital ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port. port pins can provide internal pull-up resistors (selected for each bit). the port a output buffers can sink 20 ma and can drive led dis- plays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. port a also serves as the analog inputs to the a/d converter. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors. the port b output buffers can sink 20 ma. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. port b also serves the functions of various special features of the at90s8535 as listed on page 78. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors. the port c output buffers can sink 20 ma. as inputs, port c pins that are externally pulled low will source 5 at90s/ls8535 1041h ? 11/01 current if the pull-up resistors are activated. two port c pins can alternatively be used as oscillator for timer/counter2. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors. the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. port d also serves the functions of various special features of the at90s8535 as listed on page 86. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. avcc avcc is the supply voltage pin for port a and the a/d converter. if the adc is not used, this pin must be connected to vcc. if the adc is used, this pin must be connected to vcc via a low-pass filter. see page 68 for details on operation of the adc. aref aref is the analog reference input for the a/d converter. for adc operations, a volt- age in the range 2v to av cc must be applied to this pin. agnd analog ground. if the board has a separate analog ground plane, this pin should be con- nected to this ground plane. otherwise, connect to gnd. 6 at90s/ls8535 1041h ? 11/01 clock options crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 2. either a quartz crystal or a ceramic resonator may be used. figure 2. oscillator connections note: when using the mcu oscillator as a clock for an external device, an hc buffer should be connected as indicated in the figure. external clock to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 3. figure 3. external clock drive configuration timer oscillator for the timer oscillator pins, tosc1 and tosc2, the crystal is connected directly between the pins. no external capacitors are needed. the oscillator is optimized for use with a 32,768 hz watch crystal. applying an external clock source to tosc1 is not recommended. xtal2 xtal1 gnd c2 c1 max 1 hc buffer hc 7 at90s/ls8535 1041h ? 11/01 architectural overview the fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. this means that during one single clock cycle, one arithmetic logic unit (alu) operation is executed. two operands are output from the register file, the operation is executed and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling efficient address calculations. one of the three address pointers is also used as the address pointer for the constant table look-up func- tion. these added function registers are the 16-bit x-register, y-register, and z-register. figure 4. the at90s8535 avr risc architecture the alu supports arithmetic and logic functions between registers or between a con- stant and a register. single register operations are also executed in the alu. figure 4 shows the at90s8535 avr risc microcontroller architecture. in addition to the register operation, the conventional memory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is 4k x 16 program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control interrupt unit spi unit 8-bit timer/counter watchdog timer analog to digital converter analog comparator 32 i/o lines 512 x 8 eeprom data bus 8-bit serial uart 16-bit timer/counter with pwm 8-bit timer/counter with pwm 512 x 8 data sram direct addressing indirect addressing 8 at90s/ls8535 1041h ? 11/01 assigned the 32 lowermost data space addresses ($00 - $1f), allowing them to be accessed as though they were ordinary memory locations. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, timer/counters, a/d converters and other i/o functions. the i/o memory can be accessed directly or as the data space locations following those of the register file, $20 - $5f. the avr uses a harvard architecture concept ? with separate memories and buses for program and data. the program memory is executed with a two-stage pipeline. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the pro- gram memory is in-system downloadable flash memory. with the relative jump and call instructions, the whole 4k address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram and consequently, the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the 10-bit stack pointer (sp) is read/write-accessible in the i/o space. the 512 bytes data sram can be easily accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. figure 5. memory maps a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all the different interrupts have a sepa- rate interrupt vector in the interrupt vector table at the beginning of the program 32 gen. purpose working registers 64 i/o registers internal sram (512 x 8) $0000 $001f $005f $0060 $025f $0020 $000 $fff data memory program memory program flash (4k x 16) eeprom (512 x 8) $000 $1ff data memory 9 at90s/ls8535 1041h ? 11/01 memory. the different interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. general-purpose register file figure 6 shows the structure of the 32 general-purpose working registers in the cpu. figure 6. avr cpu general-purpose working registers all the register operating instructions in the instruction set have direct and single-cycle access to all registers. the only exception is the five constant arithmetic and logic instructions sbci, subi, cpi, andi and ori between a constant and a register and the ldi instruction for load immediate constant data. these instructions apply to the second half of the registers in the register file (r16..r31). the general sbc, sub, cp, and, and or and all other operations between two registers or on a single register apply to the entire register file. as shown in figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being phys- ically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y-, and z-registers can be set to index any register in the file. 70addr. r0 $00 r1 $01 r2 $02 ? r13 $0d general r14 $0e purpose r15 $0f working r16 $10 registers r17 $11 ? r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte 10 at90s/ls8535 1041h ? 11/01 x-register, y-register and z- register the registers r26..r31 have some added functions to their general-purpose usage. these registers are address pointers for indirect addressing of the data space. the three indirect address registers, x, y, and z, are defined in figure 7. figure 7. x-, y-, and z-register in the different addressing modes, these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general- purpose working registers. within a single clock cycle, alu operations between regis- ters in the register file are executed. the alu operations are divided into three main categories: arithmetic, logical and bit functions. in-system programmable flash program memory the at90s8535 contains 8k bytes on-chip, in-system programmable flash memory for program storage. since all instructions are 16- or 32-bit words, the flash is orga- nized as 4k x 16. the flash memory has an endurance of at least 1000 write/erase cycles. the at90s8535 program counter (pc) is 12 bits wide, thus addressing the 4096 program memory addresses. see page 99 for a detailed description on flash data downloading. see page 12 for the different program memory addressing modes. 15 0 x-register 7 0 7 0 r27 ($1b) r26 ($1a) 15 0 y-register 7 0 7 0 r29 ($1d) r28 ($1c) 15 0 z-register 7 0 7 0 r31 ($1f) r30 ($1e) 11 at90s/ls8535 1041h ? 11/01 sram data memory figure 8 shows how the at90s8535 sram memory is organized. figure 8. sram organization the lower 608 data memory locations address the register file, the i/o memory and the internal data sram. the first 96 locations address the register file + i/o memory, and the next 512 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with dis- placement, indirect, indirect with pre-decrement and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode features 63 address locations reached from the base address given by the y- or z-registers. when using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y, and z are decremented and incremented. the 32 general-purpose working registers, 64 i/o registers and the 512 bytes of internal data sram in the at90s8535 are all accessible through all these addressing modes. see the next section for a detailed description of the different addressing modes. register file r0 r1 r2 r29 r30 r31 i/o registers $00 $01 $02 ... $3d $3e $3f ... $0000 $0001 $0002 $001d $001e $001f $0020 $0021 $0022 ... $005d $005e $005f ... data address space $0060 $0061 $025e $025f ... internal sram 12 at90s/ls8535 1041h ? 11/01 program and data addressing modes the at90s8535 avr risc microcontroller supports powerful and efficient addressing modes for access to the program memory (flash) and data memory (sram, register file and i/o memory). this section describes the different addressing modes supported by the avr architecture. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show the exact location of the addressing bits. register direct, single register rd figure 9. direct single register addressing the operand is contained in register d (rd). register direct, two registers rd and rr figure 10. direct register addressing, two registers operands are contained in register r (rr) and d (rd). the result is stored in register d (rd). i/o direct figure 11. i/o direct addressing operand address is contained in six bits of the instruction word. n is the destination or source register address. 13 at90s/ls8535 1041h ? 11/01 data direct figure 12. direct data addressing a 16-bit data address is contained in the 16 lsbs of a 2-word instruction. rd/rr specify the destination or source register. data indirect with displacement figure 13. data indirect with displacement operand address is the result of the y- or z-register contents added to the address con- tained in six bits of the instruction word. data indirect figure 14. data indirect addressing operand address is the contents of the x-, y-, or the z-register. op rr/rd 16 31 15 0 16 lsbs $0000 $025f 20 19 data space data space $0000 025f y or z - register op a n 0 0 5 6 10 15 15 data space $0000 $025f x, y or z - register 0 15 14 at90s/ls8535 1041h ? 11/01 data indirect with pre- decrement figure 15. data indirect addressing with pre-decrement the x-, y-, or the z-register is decremented before the operation. operand address is the decremented contents of the x-, y-, or the z-register. data indirect with post- increment figure 16. data indirect addressing with post-increment the x-, y-, or the z-register is incremented after the operation. operand address is the content of the x-, y-, or the z-register prior to incrementing. constant addressing using the lpm instruction figure 17. code memory constant addressing constant byte address is specified by the z-register contents. the 15 msbs select word address (0 - 4k), the lsb selects low byte if cleared (lsb = 0) or high byte if set (lsb = 1). data space $0000 $025f x, y or z - register 0 15 -1 data space $0000 $025f x, y or z - register 0 15 1 $fff 15 at90s/ls8535 1041h ? 11/01 indirect program addressing, ijmp and icall figure 18. indirect program memory addressing program execution continues at address contained by the z-register (i.e., the pc is loaded with the contents of the z-register). relative program addressing, rjmp and rcall figure 19. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is from - 2048 to 2047. eeprom data memory the at90s8535 contains 512 bytes of data eeprom memory. it is organized as a sep- arate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described on page 51 specifying the eeprom address registers, the eeprom data register and the eeprom control register. for the spi data downloading, see page 99 for a detailed description. memory access times and instruction execution timing this section describes the general access timing concepts for instruction execution and internal memory access. the avr cpu is driven by the system clock ? , directly generated from the external clock crystal for the chip. no internal clock division is used. figure 20 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipe- lining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks and functions per power-unit. $fff $fff +1 16 at90s/ls8535 1041h ? 11/01 figure 20. the parallel instruction fetches and instruction executions figure 21 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed and the result is stored back to the destination register. figure 21. single cycle alu operation the internal data sram access is performed in two system clock cycles as described in figure 22. figure 22. on-chip data sram access cycles system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 system clock ? total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 system clock ? wr rd data data address address t1 t2 t3 t4 prev. address read write 17 at90s/ls8535 1041h ? 11/01 i/o memory the i/o space definition of the at90s8535 is shown in table 1. table 1. at90s8535 i/o space i/o address (sram address) name function $3f ($5f) sreg status register $3e ($5e) sph stack pointer high $3d ($5d) spl stack pointer low $3b ($5b) gimsk general interrupt mask register $3a ($5a) gifr general interrupt flag register $39 ($59) timsk timer/counter interrupt mask register $38 ($58) tifr timer/counter interrupt flag register $35 ($55) mcucr mcu general control register $34 ($45) mcusr mcu general status register $33 ($53) tccr0 timer/counter0 control register $32 ($52) tcnt0 timer/counter0 (8-bit) $2f ($4f) tccr1a timer/counter1 control register a $2e ($4e) tccr1b timer/counter1 control register b $2d ($4d) tcnt1h timer/counter1 high byte $2c ($4c) tcnt1l timer/counter1 low byte $2b ($4b) ocr1ah timer/counter1 output compare register a high byte $2a ($4a) ocr1al timer/counter1 output compare register a low byte $29 ($49) ocr1bh timer/counter1 output compare register b high byte $28 ($48) ocr1bl timer/counter1 output compare register b low byte $27 ($47) icr1h t/c 1 input capture register high byte $26 ($46) icr1l t/c 1 input capture register low byte $25 ($45) tccr2 timer/counter2 control register $24 ($44) tcnt2 timer/counter2 (8-bit) $23 ($43) ocr2 timer/counter2 output compare register $22 ($42) assr asynchronous mode status register $21 ($41) wdtcr watchdog timer control register $1f ($3e) eearh eeprom address register high byte $1e ($3e) eearl eeprom address register low byte $1d ($3d) eedr eeprom data register $1c ($3c) eecr eeprom control register $1b ($3b) porta data register, port a $1a ($3a) ddra data direction register, port a $19 ($39) pina input pins, port a $18 ($38) portb data register, port b 18 at90s/ls8535 1041h ? 11/01 note: reserved and unused locations are not shown in the table. all at90s8535 i/os and peripherals are placed in the i/o space. the i/o locations are accessed by the in and out instructions transferring data between the 32 general-pur- pose working registers and the i/o space. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set section for more details. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o registers as sram, $20 must be added to these addresses. all i/o register addresses throughout this document are shown with the sram address in parentheses. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical ? 1 ? to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a ? 1 ? back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers $00 to $1f only. the i/o and peripherals control registers are explained in the following sections. $17 ($37) ddrb data direction register, port b $16 ($36) pinb input pins, port b $15 ($35) portc data register, port c $14 ($34) ddrc data direction register, port c $13 ($33) pinc input pins, port c $12 ($32) portd data register, port d $11 ($31) ddrd data direction register, port d $10 ($30) pind input pins, port d $0f ($2f) spdr spi i/o data register $0e ($2e) spsr spi status register $0d ($2d) spcr spi control register $0c ($2c) udr uart i/o data register $0b ($2b) usr uart status register $0a ($2a) ucr uart control register $09 ($29) ubrr uart baud rate register $08 ($28) acsr analog comparator control and status register $07 ($27) admux adc multiplexer select register $06 ($26) adcsr adc control and status register $05 ($25) adch adc data register high $04 ($24) adcl adc data register low table 1. at90s8535 i/o space (continued) i/o address (sram address) name function 19 at90s/ls8535 1041h ? 11/01 status register ? sreg the avr status register (sreg) at i/o space location $3f ($5f) is defined as: bit 7 ? i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared (zero), none of the interrupts are enabled inde- pendent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred and is set by the reti instruction to enable subsequent interrupts. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source and destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 ? h: half-carry flag the half-carry flag h indicates a half-carry in some arithmetic operations. see the instruction set description for detailed information. bit 4 ? s: sign bit, s = n ? v the s-bit is always an exclusive or between the negative flag n and the two ? s comple- ment overflow flag v. see the instruction set description for detailed information. bit 3 ? v: two ? s complement overflow flag the two ? s complement overflow flag v supports two ? s complement arithmetics. see the instruction set description for detailed information. bit 2 ? n: negative flag the negative flag n indicates a negative result from an arithmetical or logical operation. see the instruction set description for detailed information. bit 1 ? z: zero flag the zero flag z indicates a zero result from an arithmetical or logic operation. see the instruction set description for detailed information. bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetical or logical operation. see the instruc- tion set description for detailed information. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. bit 76543210 $3f ($5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 20 at90s/ls8535 1041h ? 11/01 stack pointer ? sp the at90s8535 stack pointer is implemented as two 8-bit registers in the i/o space locations $3e ($5e) and $3d ($5d). as the at90s8535 data memory has $25f loca- tions, 10 bits are used. the stack pointer points to the data sram stack area where the subroutine and inter- rupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above $60. the stack pointer is decremented by 1 when data is pushed onto the stack with the push instruction and it is decremented by 2 when an address is pushed onto the stack with subroutine calls and interrupts. the stack pointer is incremented by 1 when data is popped from the stack with the pop instruction and it is incremented by 2 when an address is popped from the stack with return from subroutine ret or return from interrupt reti. reset and interrupt handling the at90s8535 provides 16 different interrupt sources. these interrupts and the sepa- rate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits that must be set (one) together with the i-bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 2. the list also determines the priority levels of the different interrupts. the lower the address, the higher the priority level. reset has the highest priority, and next is int0 (the external interrupt request 0), etc. bit 151413121110 9 8 $3e ($5e) ?????? sp9 sp8 sph $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/writerrrrrrr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 table 2. reset and interrupt vectors vector no. program address source interrupt definition 1 $000 reset hardware pin, power-on reset and watchdog reset 2 $001 int0 external interrupt request 0 3 $002 int1 external interrupt request 1 4 $003 timer2 comp timer/counter2 compare match 5 $004 timer2 ovf timer/counter2 overflow 6 $005 timer1 capt timer/counter1 capture event 7 $006 timer1 compa timer/counter1 compare match a 8 $007 timer1 compb timer/counter1 compare match b 9 $008 timer1 ovf timer/counter1 overflow 10 $009 timer0 ovf timer/counter0 overflow 11 $00a spi, stc spi serial transfer complete 12 $00b uart, rx uart, rx complete 21 at90s/ls8535 1041h ? 11/01 the most typical and general program setup for the reset and interrupt vector addresses are: address labels code comments $000 rjmp reset ; reset handler $001 rjmp ext_int0 ; irq0 handler $002 rjmp ext_int1 ; irq1 handler $003 rjmp tim2_comp ; timer2 compare handler $004 rjmp tim2_ovf ; timer2 overflow handler $005 rjmp tim1_capt ; timer1 capture handler $006 rjmp tim1_compa ; timer1 comparea handler $007 rjmp tim1_compb ; timer1 compareb handler $008 rjmp tim1_ovf ; timer1 overflow handler $009 rjmp tim0_ovf ; timer0 overflow handler $00a rjmp spi_stc; ; spi transfer complete handler $00b rjmp uart_rxc ; uart rx complete handler $00c rjmp uart_dre ; udr empty handler $00d rjmp uart_txc ; uart tx complete handler $00e rjmp adc ; adc conversion complete interrupt handler $00f rjmp ee_rdy ; eeprom ready handler $010 rjmp ana_comp ; analog comparator handler $011 main: ldi r16, high(ramend); main program start $012 out sph,r16 $013 ldi r16, low(ramend) ; $014 out spl,r16 $015 22 at90s/ls8535 1041h ? 11/01 placed at these locations. the circuit diagram in figure 23 shows the reset logic. table 3 defines the timing and electrical parameters of the reset circuitry. figure 23. reset logic note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling). power-on reset a power-on reset (por) circuit ensures that the device is reset from power-on. as shown in figure 23, an internal timer clocked from the watchdog timer oscillator pre- vents the mcu from starting until after a certain period after v cc has reached the power- on threshold voltage (v pot ), regardless of the v cc rise time (see figure 24). the user can select the start-up time according to typical oscillator start-up time. the number of wdt oscillator cycles is shown in table 4. the frequency of the watchdog oscillator is voltage-dependent as shown in ? typical characteristics ? on page 107. if the built-in start-up delay is sufficient, reset can be connected to v cc directly or via an external pull-up resistor. by holding the pin low for a period after v cc has been applied, the power-on reset period can be extended. refer to figure 25 for a timing example of this. table 3. reset characteristics (v cc = 5.0v) symbol parameter min typ max units v pot (1) power-on reset threshold (rising) 1.0 1.4 1.8 v power-on reset threshold (falling) 0.4 0.6 0.8 v v rst reset pin threshold voltage 0.6 v cc v t tout reset delay time-out period fstrt unprogrammed 11.0 16.0 21.0 ms t tout reset delay time-out period fstrt programmed 1.0 1.1 1.2 ms table 4. number of watchdog oscillator cycles fstrt time-out at v cc = 5v number of wdt cycles programmed 1.1 ms 1k unprogrammed 16.0 ms 16k 23 at90s/ls8535 1041h ? 11/01 figure 24. mcu start-up, reset tied to v cc . figure 25. mcu start-up, reset controlled externally external reset an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage (v rst ) on its positive edge, the delay timer starts the mcu after the time-out period t tout has expired. figure 26. external reset during operation vcc reset time-out internal reset t tout v pot v rst vcc reset time-out internal reset t tout v pot v rst 24 at90s/ls8535 1041h ? 11/01 watchdog reset when the watchdog times out, it will generate a short reset pulse of 1 xtal cycle dura- tion. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 49 for details on operation of the watchdog. figure 27. watchdog reset during operation mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. bits 7..2 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read as zero. bit 1 ? extrf: external reset flag after a power-on reset, this bit is undefined (x). it can only be set by an external reset. a watchdog reset will leave this bit unchanged. the bit is cleared by writing a logical zero to the bit. bit 0 ? porf: power-on reset flag this bit is only set by a power-on reset. a watchdog reset or an external reset will leave this bit unchanged. the bit is cleared by writing a logical zero to the bit. to summarize, table 5 shows the value of these two bits after the three modes of reset. to make use of these bits to identify a reset condition, the user software should clear both the porf and extrf bits as early as possible in the program. checking the porf and extrf values is done before the bits are cleared. if the bit is cleared before an external or watchdog reset occurs, the source of reset can be found by using table 6. bit 76543210 $34 ($54) ?????? extrf porf mcusr read/writerrrrrrr/wr/w initial value000000see bit description table 5. porf and extrf values after reset reset source extrf porf power-on reset undefined 1 external reset 1 unchanged watchdog reset unchanged unchanged 25 at90s/ls8535 1041h ? 11/01 interrupt handling the at90s8535 has two 8-bit interrupt mask control registers: gimsk (general inter- rupt mask register) and timsk (timer/counter interrupt mask register). when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all inter- rupts are disabled. the user software can set (one) the i-bit to enable nested interrupts. the i-bit is set (one) when a return from interrupt instruction (reti) is executed. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logical ? 1 ? to the flag bit position(s) to be cleared. if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software. if one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one) and will be executed by order of priority. note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. general interrupt mask register ? gimsk bit 7 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the mcu general control register (mcucr) define whether the external interrupt is activated on rising or falling edge of the int1 pin or level sensed. activity on the pin will cause an interrupt request even if int1 is configured as an output. the corre- sponding interrupt of external interrupt request 1 is executed from program memory address $002. see also ? external interrupts. ? bit 6 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control register (mcucr) define whether the external interrupt is activated on rising or falling edge of the int0 pin or level sensed. activity on the pin will cause an interrupt request even if int0 is configured as an output. the corre- table 6. reset source identification extrf porf reset source 0 0 watchdog reset 0 1 power-on reset 1 0 external reset 1 1 power-on reset bit 7 6 5 4 3 2 1 0 $3b ($5b) int1 int0 ?? ???? gimsk read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 26 at90s/ls8535 1041h ? 11/01 sponding interrupt of external interrupt request 0 is executed from program memory address $001. see also ? external interrupts. ? bits 5.0 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read as zero. general interrupt flag register ? gifr bit 7 ? intf1: external interrupt flag1 when an edge or logical change on the int1 pin triggers an interrupt request, intf1 becomes set (one). this flag is always cleared (0) when the pin is configured for low- level interrupts, as the state of a low-level interrupt can be determined by reading the pin register. if the i-bit in sreg and the int1 bit in gimsk are set (one), the mcu will jump to the interrupt address $002. for edge and logic change interrupts, this flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logi- cal ? 1 ? to it. bit 6 ? intf0: external interrupt flag0 when an edge or logical change on the int0 pin triggers an interrupt request, intf0 becomes set (one). this flag is always cleared (0) when the pin is configured for low- level interrupts, as the state of a low-level interrupt can be determined by reading the pin register. if the i-bit in sreg and the int0 bit in gimsk are set (one), the mcu will jump to the interrupt address $001. for edge and logic change interrupts, this flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logi- cal ? 1 ? to it. bits 5..0 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read as zero. timer/counter interrupt mask register ? timsk bit 7 ? ocie2: timer/counter2 output compare match interrupt enable when the ocie2 bit is set (one) and the i-bit in the status register is set (one), the timer/counter2 compare match interrupt is enabled. the corresponding interrupt (at vector $003) is executed if a compare match in timer/counter2 occurs (i.e., when the ocf2 bit is set in the timer/counter interrupt flag register [tifr]). bit 6 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is set (one) and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the corresponding interrupt (at vector $004) is executed if an overflow in timer/counter2 occurs (i.e., when the tov2 bit is set in the timer/counter interrupt flag register [tifr]). bit 7 6 5 4 3 2 1 0 $3a ($5a) intf1 intf0 ?? ???? gifr read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $39 ($59) ocie2 toie2 ticie1 ocie1a ocie1b toie1 ? toie0 timsk read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 27 at90s/ls8535 1041h ? 11/01 bit 5 ? ticie1: timer/counter1 input capture interrupt enable when the ticie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 input capture event interrupt is enabled. the corresponding interrupt (at vector $005) is executed if a capture-triggering event occurs on pin 20, pd6 (icp) (i.e., when the icf1 bit is set in the timer/counter interrupt flag register [tifr]). bit 4 ? ocie1a: timer/counter1 output comparea match interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 comparea match interrupt is enabled. the corresponding interrupt (at vector $006) is executed if a comparea match in timer/counter1 occurs (i.e., when the ocf1a bit is set in the timer/counter interrupt flag register [tifr]). bit 3 ? ocie1b: timer/counter1 output compareb match interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compareb match interrupt is enabled. the corresponding interrupt (at vector $007) is executed if a compareb match in timer/counter1 occurs (i.e., when the ocf1b bit is set in the timer/counter interrupt flag register [tifr]). bit 2 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $008) is executed if an overflow in timer/counter1 occurs (i.e., when the tov1 bit is set in the timer/counter interrupt flag register [tifr]). bit 1 ? res: reserved bit this bit is a reserved bit in the at90s8535 and always reads zero. bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $009) is executed if an overflow in timer/counter0 occurs (i.e., when the tov0 bit is set in the timer/counter interrupt flag register [tifr]). timer/counter interrupt flag register ? tifr bit 7 ? ocf2: output compare flag 2 the ocf2 bit is set (one) when compare match occurs between the timer/counter2 and the data in ocr2 (output compare register2). ocf2 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2 is cleared by writing a logical ? 1 ? to the flag. when the i-bit in sreg and ocie2 (timer/counter2 compare match interrupt enable) and the ocf2 are set (one), the timer/counter2 compare match interrupt is executed. bit 6 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs in timer/counter2. tov2 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logical ? 1 ? to the flag. when the sreg i-bit and toie2 (timer/counter2 overflow interrupt enable) and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in up/down pwm mode, this bit is set when timer/counter1 advances from $0000. bit 7 6 5 4 3 2 1 0 $38 ($58) ocf2 tov2 icf1 ocf1a ocf1b tov1 ? tov0 tifr read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 28 at90s/ls8535 1041h ? 11/01 bit 5 ? icf1: input capture flag 1 the icf1 bit is set (one) to flag an input capture event, indicating that the timer/counter1 value has been transferred to the input capture register (icr1). icf1 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, icf1 is cleared by writing a logical ? 1 ? to the flag. when the sreg i-bit and ticie1 (timer/counter1 input capture interrupt enable) and icf1 are set (one), the timer/counter1 capture interrupt is executed. bit 4 ? ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1a (output compare register 1a). ocf1a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf1a is cleared by writing a logical ? 1 ? to the flag. when the i-bit in sreg and ocie1a (timer/counter1 compare match interrupta enable) and the ocf1a are set (one), the timer/counter1 compare a match interrupt is executed. bit 3 ? ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1b (output compare register 1b). ocf1b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf1b is cleared by writing a logical ? 1 ? to the flag. when the i-bit in sreg and ocie1b (timer/counter1 compare match interruptb enable) and the ocf1b are set (one), the timer/counter1 compare match b interrupt is executed. bit 2 ? tov1: timer/counter1 overflow flag the tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov1 is cleared by writing a logical ? 1 ? to the flag. when the i-bit in sreg and toie1 (timer/counter1 overflow interrupt enable) and tov1 are set (one), the timer/counter1 overflow interrupt is executed. in up/down pwm mode, this bit is set when timer/counter1 advances from $0000. bit 1 ? res: reserved bit this bit is a reserved bit in the at90s8535 and always reads zero. bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logical ? 1 ? to the flag. when the sreg i-bit and toie0 (timer/counter0 overflow interrupt enable) and tov0 are set (one), the timer/counter0 overflow interrupt is executed. in up/down pwm mode, this bit is set when timer/counter1 advances from $0000. external interrupts the external interrupts are triggered by the int1 and int0 pins. observe that, if enabled, the interrupts will trigger even if the int0/int1 pins are configured as outputs. this feature provides a way of generating a software interrupt. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the mcu control register (mcucr). when the external interrupt is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is held low. the external interrupts are set up as described in the specification for the mcu control register (mcucr). 29 at90s/ls8535 1041h ? 11/01 interrupt response time the interrupt execution response for all the enabled avr interrupts is four clock cycles minimum. four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. during this 4-clock-cycle period, the program counter (2 bytes) is pushed onto the stack and the stack pointer is decremented by 2. the vector is normally a relative jump to the interrupt routine and this jump takes two clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. a return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. during these four clock cycles, the program counter (2 bytes) is popped back from the stack, the stack pointer is incremented by 2 and the i-flag in sreg is set. when the avr exits from an interrupt, it will always return to the main pro- gram and execute one more instruction before any pending interrupt is served. mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. bit 7 ? res: reserved bit this bit is a reserved bit in the at90s8535 and always reads zero. bit 6 ? se: sleep enable the se bit must be set (one) to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the pro- grammer ? s purpose, it is recommended to set the sleep enable (se) bit just before the execution of the sleep instruction. bits 5, 4 ? sm1/sm0: sleep mode select bits 1 and 0 these bits select between the three available sleep modes as shown in table 7. bits 3, 2 ? isc11, isc10: interrupt sense control 1 bits 1 and 0 the external interrupt 1 is activated by the external pin int1 if the sreg i-flag and the corresponding interrupt mask in the gimsk is set. the level and edges on the external int1 pin that activate the interrupt are defined in table 8. bit 76543210 $35 ($55) ? se sm1 sm0 isc11 isc10 isc01 isc00 mcucr read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 7. sleep mode select sm1 sm0 sleep mode 00idle 01reserved 1 0 power-down 11power save 30 at90s/ls8535 1041h ? 11/01 the value on the int pin is sampled before detecting edges. if edge interrupt is selected, pulses that last longer than one cpu clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. bit 1, 0 ? isc01, isc00: interrupt sense control 0 bits 1 and 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corresponding interrupt mask is set. the level and edges on the external int0 pin that activate the interrupt are defined in table 9. the value on the int pin is sampled before detecting edges. if edge interrupt is selected, pulses that last longer than one cpu clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. sleep modes to enter any of the three sleep modes, the se bit in mcucr must be set (one) and a sleep instruction must be executed. the sm0 and sm1 bits in the mcucr register select which sleep mode (idle, power-down or power save) will be activated by the sleep instruction. see table 7. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up, executes the interrupt routine and resumes execution from the instruction following sleep. the contents of the register file, sram and i/o memory are unaltered. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. idle mode when the sm1/sm0 bits are set to 00, the sleep instruction makes the mcu enter the idle mode, stopping the cpu but allowing spi, uarts, analog comparator, adc, timer/counters, watchdog and the interrupt system to continue operating. this enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and uart receive complete interrupts. if wake-up from the analog table 8. interrupt 1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 01reserved 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request. table 9. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 01reserved 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 31 at90s/ls8535 1041h ? 11/01 comparator interrupt is not required, the analog comparator can be powered down by setting the acd-bit in the analog comparator control and status register (acsr). this will reduce power consumption in idle mode. when the mcu wakes up from idle mode, the cpu starts program execution immediately. power-down mode when the sm1/sm0 bits are set to 10, the sleep instruction makes the mcu enter the power-down mode. in this mode, the external oscillator is stopped while the external interrupts and the watchdog (if enabled) continue operating. only an external reset, a watchdog reset (if enabled) or an external level interrupt can wake up the mcu. note that when a level-triggered interrupt is used for wake-up from power-down, the low level must be held for a time longer than the reset delay time-out period t tout . when waking up from power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is equal to the reset period, as shown in table 3 on page 22. if the wake-up condition disappears before the mcu wakes up and starts to execute, e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be executed. power save mode when the sm1/sm0 bits are 11, the sleep instruction makes the mcu enter the power save mode. this mode is identical to power-down, with one exception: if timer/counter2 is clocked asynchronously, i.e., the as2 bit in assr is set, timer/counter2 will run during sleep. in addition to the power-down wake-up sources, the device can also wake up from either a timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk and the global interrupt enable bit in sreg is set. when waking up from power save mode by an external interrupt, two instruction cycles are executed before the interrupt flags are updated. when waking up by the asynchro- nous timer, three instruction cycles are executed before the flags are updated. during these cycles, the processor executes instructions, but the interrupt condition is not read- able and the interrupt routine has not started yet. when waking up from power save mode by an asynchronous timer interrupt, the part will wake up even if global interrupts are disabled. to ensure that the part executes the interrupt routine when waking up, also set the global interrupt enable bit in sreg. if the asynchronous timer is not clocked asynchronously, power-down mode is recom- mended instead of power save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in power save mode, even if as2 is 0. 32 at90s/ls8535 1041h ? 11/01 timer/counters the at90s8535 provides three general-purpose timer/counters ? two 8-bit t/cs and one 16-bit t/c. timer/counter2 can optionally be asynchronously clocked from an exter- nal oscillator. this oscillator is optimized for use with a 32.768 khz watch crystal, enabling use of timer/counter2 as a real-time clock (rtc). timer/counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. timer/counter2 has its own prescaler. these timer/counters can either be used as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. timer/counter prescalers figure 28. prescaler for timer/counter0 and 1 for timer/counters 0 and 1, the four different prescaled selections are: ck/8, ck/64, ck/256 and ck/1024, where ck is the oscillator clock. for the two timer/counters 0 and 1, ck, external source and stop can also be selected as clock sources. figure 29. timer/counter2 prescaler tck1 tck0 10-bit t/c prescaler timer/counter2 clock source tck2 ck pck2 tosc1 as2 cs20 cs21 cs22 pck2/8 pck2/64 pck2/128 pck2/1024 pck2/256 pck2/32 0 33 at90s/ls8535 1041h ? 11/01 the clock source for timer/counter2 prescaler is named pck2. pck2 is by default con- nected to the main system clock (ck). by setting the as2 bit in assr, timer/counter2 prescaler is asynchronously clocked from the pc6(tosc1) pin. this enables use of timer/counter2 as a real-time clock (rtc). when as2 is set, pins pc6(tosc1) and pc7(tosc2) are disconnected from port c. a crystal can then be connected between the pc6(tosc1) and pc7(tosc2) pins to serve as an independent clock source for timer/counter2. the oscillator is optimized for use with a 32.768 khz crystal. applying an external clock source to tosc1 is not recommended. 8-bit timer/counter0 figure 30 shows the block diagram for timer/counter0. the 8-bit timer/counter0 can select clock source from ck, prescaled ck or an external pin. in addition, it can be stopped as described in the specification for the timer/counter0 control register (tccr0). the overflow status flag is found in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter0 control register (tccr0). the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register (timsk). when timer/counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. similarly, the high prescaling opportunities make the timer/counter0 useful for lower speed functions or exact timing functions with infre- quent actions. figure 30. timer/counter0 block diagram 8-bit da ta bus t/c0 control register (tccr0) timer/counter0 (tcnt0) 0 7 t/c clk source control logic cs02 cs01 cs00 ck t/c0 over- flow irq timer int. mask register (timsk) toie0 toie1 ocie1a ocie1b ticie1 toie2 ocie2 timer int. flag register (tifr) tov0 tov1 ocf1a ocf1b icf1 tov2 ocf2 t0 34 at90s/ls8535 1041h ? 11/01 timer/counter0 control register ? tccr0 bits 7..3 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read zero. bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bits 2, 1 and 0 the clock select0 bits 2,1 and 0 define the prescaling source of timer/counter0. the stop condition provides a timer enable/disable function. the prescaled ck modes are scaled directly from the ck oscillator clock. if the external pin modes are used, the corresponding setup must be performed in the actual data direction control register (cleared to zero gives an input pin). timer counter 0 ? tcnt0 the timer/counter0 is realized as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the clock cycle following the write operation. bit 7 6 5 4 3 210 $33 ($53) ?? ? ? ? cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 10. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, timer/counter0 is stopped. 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge bit 76543210 $32 ($52) msb lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 35 at90s/ls8535 1041h ? 11/01 16-bit timer/counter1 figure 31 shows the block diagram for timer/counter1. figure 31. timer/counter1 block diagram the 16-bit timer/counter1 can select clock source from ck, prescaled ck or an exter- nal pin. in addition, it can be stopped as described in the specification for the timer/counter1 control registers (tccr1a and tccr1b). the different status flags (overflow, compare match and capture event) and control signals are found in the timer/counter1 control registers (tccr1a and tccr1b). the interrupt enable/dis- able settings for timer/counter1 are found in the timer/counter interrupt mask register (timsk). when timer/counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 16-bit timer/counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. similarly, the high prescaling opportunities makes the timer/counter1 useful for lower speed functions or exact timing functions with infrequent actions. the timer/counter1 supports two output compare functions using the output compare register 1a and b (ocr1a and ocr1b) as the data sources to be compared to the timer/counter1 contents. the output compare functions include optional clearing of 8-bit da ta bus t/c1 control register b (tccr1b) t/c1 control register a (tccr1a) t/c1 input capture register (icr1) 16 bit comparator 16 bit comparator timer/counter1 output compare register a timer/counter1 output compare register b timer/counter1 (tcnt1) timer int. flag register (tifr) 0 0 0 0 0 0 7 7 7 7 7 7 8 8 8 8 8 8 15 15 15 15 15 15 control logic com1a1 com1b1 cs12 tov1 tov1 tov0 ocf1a ocf1a ocf1b ocf1b icf1 icf1 com1a0 com1b0 cs1 1 ctc1 pwm1 1 pwm10 ices1 icnc1 cs10 c k t/c1 compare matcha irq t/c1 compare matchb irq t/c1 input capture irq t/c1 over- flow irq capture trigger t/c clock source t/c clear up/down timer int. mask register (timsk) toie0 toie1 ocie1a ocie1b ticie1 toie2 tov2 ocie2 ocf2 t1 36 at90s/ls8535 1041h ? 11/01 the counter on comparea match and actions on the output compare pins on both com- pare matches. timer/counter1 can also be used as an 8-, 9- or 10-bit pulse width modulator. in this mode the counter and the ocr1a/ocr1b registers serve as a dual glitch-free stand- alone pwm with centered pulses. refer to page 40 for a detailed description of this function. the input capture function of timer/counter1 provides a capture of the timer/counter1 contents to the input capture register (icr1), triggered by an external event on the input capture pin (icp). the actual capture event settings are defined by the timer/counter1 control register (tccr1b). in addition, the analog comparator can be set to trigger the input capture. refer to ? analog comparator ? on page 66 for details on this. the icp pin logic is shown in figure 32. figure 32. icp pin schematic diagram if the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples and all four must be equal to activate the capture flag. the input pin signal is sampled at xtal clock frequency. timer/counter1 control register a ? tccr1a bits 7, 6 ? com1a1, com1a0: compare output mode1a, bits 1 and 0 the com1a1 and com1a0 control bits determine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1a (output comparea pin 1). this is an alternative function to an i/o port and the corresponding direction control bit must be set (one) to control an output pin. the control configuration is shown in table 11. bits 5, 4 ? com1b1, com1b0: compare output mode1b, bits 1 and 0 the com1b1 and com1b0 control bits determine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1b (output compareb). this is an alternative function to an i/o port and the corresponding direction control bit must be set (one) to control an output pin. the control configuration is given in table 11. bit 7 6 5 4 3 2 1 0 $2f ($4f) com1a1 com1a0 com1b1 com1b0 ?? pwm11 pwm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 37 at90s/ls8535 1041h ? 11/01 note: x = a or b. in pwm mode, these bits have a different function. refer to table 15 for a detailed description. when changing the com1x1/com1x0 bits, output compare interrupt 1 must be disabled by clearing their interrupt enable bits in the timsk register. other- wise an interrupt can occur when the bits are changed. bits 3..2 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read zero. bits 1..0 ? pwm11, pwm10: pulse width modulator select bits these bits select pwm operation of timer/counter1 as specified in table 12. this mode is described on page 40. timer/counter1 control register b ? tccr1b bit 7 ? icnc1: input capture1 noise canceler (4 cks) when the icnc1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. the input capture is triggered at the first rising/falling edge sampled on the icp (input capture pin) as specified. when the icnc1 bit is set (one), four successive samples are measured on the icp (input capture pin), and all samples must be high/low according to the input capture trigger specification in the ices1 bit. the actual sampling frequency is xtal clock frequency. bit 6 ? ices1: input capture1 edge select while the ices1 bit is cleared (zero), the timer/counter1 contents are transferred to the input capture register (icr1) on the falling edge of the input capture pin (icp). while the ices1 bit is set (one), the timer/counter1 contents are transferred to the input cap- ture register (icr1) on the rising edge of the input capture pin (icp). bits 5, 4 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read zero. table 11. compare 1 mode select com1x1 com1x0 description 0 0 timer/counter1 disconnected from output pin oc1x 0 1 toggle the oc1x output line. 1 0 clear the oc1x output line (to zero). 1 1 set the oc1x output line (to one). table 12. pwm mode select pwm11 pwm10 description 0 0 pwm operation of timer/counter1 is disabled 0 1 timer/counter1 is an 8-bit pwm 1 0 timer/counter1 is a 9-bit pwm 1 1 timer/counter1 is a 10-bit pwm bit 7654 3210 $2e ($4e) icnc1 ices1 ?? ctc1 cs12 cs11 cs10 tccr1b read/write r/w r/w r r r/w r/w r/w r/w initial value0000 0000 38 at90s/ls8535 1041h ? 11/01 bit 3 ? ctc1: clear timer/counter1 on compare match when the ctc1 control bit is set (one), the timer/counter1 is reset to $0000 in the clock cycle after a comparea match. if the ctc1 control bit is cleared, timer/counter1 contin- ues counting and is unaffected by a compare match. since the compare match is detected in the cpu clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. when a prescaling of 1 is used and the comparea register is set to c, the timer will count as follows if ctc1 is set: ... | c-2 | c-1 | c | 0 | 1 |... when the prescaler is set to divide by 8, the timer will count like this: ... | c-2, c-2, c-2, c-2, c-2, c-2, c-2, c-2 | c-1, c-1, c-1, c-1, c-1, c-1, c-1, c-1 | c, 0, 0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|... in pwm mode, this bit has no effect. bits 2, 1, 0 ? cs12, cs11, cs10: clock select1, bits 2, 1 and 0 the clock select1 bits 2, 1 and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. the ck down divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used, the corresponding setup must be performed in the actual direction control regis- ter (cleared to zero gives an input pin). timer/counter1 ? tcnt1h and tcnt1l this 16-bit register contains the prescaled value of the 16-bit timer/counter1. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary regis- ter (temp). this temporary register is also used when accessing ocr1a, ocr1b and icr1. if the main program and also interrupt routines perform access to registers using table 13. clock 1 prescale select cs12 cs11 cs10 description 0 0 0 stop, the timer/counter1 is stopped. 001ck 010ck/8 011ck/64 100ck/256 1 0 1 ck/1024 1 1 0 external pin t1, falling edge 1 1 1 external pin t1, rising edge bit 151413121110 9 8 $2d ($4d) msb tcnt1h $2c ($4c) lsb tcnt1l 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 39 at90s/ls8535 1041h ? 11/01 temp, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routines). tcnt1 timer/counter1 write: when the cpu writes to the high byte tcnt1h, the written data is placed in the temp register. next, when the cpu writes the low byte tcnt1l, this byte of data is combined with the byte data in the temp register, and all 16 bits are written to the tcnt1 timer/counter1 register simultaneously. consequently, the high byte tcnt1h must be accessed first for a full 16-bit register write operation. tcnt1 timer/counter1 read: when the cpu reads the low byte tcnt1l, the data of the low byte tcnt1l is sent to the cpu and the data of the high byte tcnt1h is placed in the temp register. when the cpu reads the data in the high byte tcnt1h, the cpu receives the data in the temp register. consequently, the low byte tcnt1l must be accessed first for a full 16-bit register read operation. the timer/counter1 is realized as an up or up/down (in pwm mode) counter with read and write access. if timer/counter1 is written to and a clock source is selected, the timer/counter1 continues counting in the timer clock cycle after it is preset with the writ- ten value. timer/counter1 output compare register ? ocr1ah and ocr1al timer/counter1 output compare register ? ocr1bh and ocr1bl the output compare registers are 16-bit read/write registers. the timer/counter1 output compare registers contain the data to be continuously com- pared with timer/counter1. actions on compare matches are specified in the timer/counter1 control and status registers. a compare match only occurs if timer/counter1 counts to the ocr value. a software write that sets tcnt1 and ocr1a or ocr1b to the same value does not generate a compare match. a compare match will set the compare interrupt flag in the cpu clock cycle following the compare event. since the output compare registers (ocr1a and ocr1b) are 16-bit registers, a tem- porary register (temp) is used when ocr1a/b are written to ensure that both bytes are updated simultaneously. when the cpu writes the high byte, ocr1ah or ocr1bh, the data is temporarily stored in the temp register. when the cpu writes the low byte, bit 151413121110 9 8 $2b ($4b) msb ocr1ah $2a ($4a) lsb ocr1al 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 bit 151413121110 9 8 $29 ($49) msb ocr1bh $28 ($48) lsb ocr1bl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 40 at90s/ls8535 1041h ? 11/01 ocr1al or ocr1bl, the temp register is simultaneously written to ocr1ah or ocr1bh. consequently, the high byte ocr1ah or ocr1bh must be written first for a full 16-bit register write operation. the temp register is also used when accessing tcnt1 and icr1. if the main program and interrupt routines perform access to registers using temp, interrupts must be dis- abled during access from the main program. timer/counter1 input capture register ? icr1h and icr1l the input capture register is a 16-bit read-only register. when the rising or falling edge (according to the input capture edge setting [ices1]) of the signal at the input capture pin (icp) is detected, the current value of the timer/counter1 is transferred to the input capture register (icr1). at the same time, the input capture flag (icf1) is set (one). since the input capture register (icr1) is a 16-bit register, a temporary register (temp) is used when icr1 is read to ensure that both bytes are read simultaneously. when the cpu reads the low byte icr1l, the data is sent to the cpu and the data of the high byte icr1h is placed in the temp register. when the cpu reads the data in the high byte icr1h, the cpu receives the data in the temp register. consequently, the low-byte icr1l must be accessed first for a full 16-bit register read operation. the temp register is also used when accessing tcnt1, ocr1a and ocr1b. if the main program and interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program. timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1, the output compare register1a (ocr1a) and the output compare register1b (ocr1b) form a dual 8-, 9- or 10-bit, free-running, glitch-free and phase-correct pwm with outputs on the pd5(oc1a) and pd4(oc1b) pins. timer/counter1 acts as an up/down counter, counting up from $0000 to top (see table 14), where it turns and counts down again to zero before the cycle is repeated. when the counter value matches the contents of the 10 least significant bits of ocr1a or ocr1b, the pd5(oc1a)/pd4(oc1b) pins are set or cleared according to the settings of the com1a1/com1a0 or com1b1/com1b0 bits in the timer/counter1 control register (tccr1a). refer to table 15 for details. note that if the compare register contains the top value and the prescaler is not in use (cs12..cs10 = 001), the pwm output will not produce any pulse at all, because the bit 151413121110 9 8 $27 ($47) msb icr1h $26 ($46) lsb icr1l 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 table 14. timer top values and pwm frequency pwm resolution timer top value frequency 8-bit $00ff (255) f tck1 /510 9-bit $01ff (511) f tck1 /1022 10-bit $03ff(1023) f tck1 /2046 41 at90s/ls8535 1041h ? 11/01 up-counting and down-counting values are reached simultaneously. when the prescaler is in use (cs12..cs10 001 or 000), the pwm output goes active when the counter reaches top value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the top value, making a one-period pwm pulse. note: x = a or b note that in the pwm mode, the 10 least significant ocr1a/ocr1b bits, when written, are transferred to a temporary location. they are latched when timer/counter1 reaches the value top. this prevents the occurrence of odd-length pwm pulses (glitches) in the event of an unsynchronized ocr1a/ocr1b write. see figure 33 for an example. figure 33. effects of unsynchronized ocr1 latching during the time between the write and the latch operations, a read from ocr1a or ocr1b will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a/b. when the ocr1a/ocr1b contains $0000 or top, the output oc1a/oc1b is updated to low or high on the next compare match according to the settings of com1a1/com1a0 or com1b1/com1b0. this is shown in table 16. table 15. compare1 mode select in pwm mode com1x1 com1x0 effect on ocx1 0 0 not connected 0 1 not connected 10 cleared on compare match, up-counting. set on compare match, down-counting (non-inverted pwm). 11 cleared on compare match, down-counting. set on compare match, up-counting (inverted pwm). table 16. pwm outputs ocr1x = $0000 or top com1x1 com1x0 ocr1x output oc1x 1 0 $0000 l counter v alue compare v alue pwm output oc1x synchronized ocr1x latch counter value compare value pwm output oc1x unsynchronized ocr1x latch glitch compare value changes note: x = a or b compare v alue changes 42 at90s/ls8535 1041h ? 11/01 note: x = a in pwm mode, the timer overflow flag1 (tov1) is set when the counter advances from $0000. timer overflow interrupt1 operates exactly as in normal timer/counter mode, i.e., it is executed when tov1 is set, provided that timer overflow interrupt1 and global interrupts are enabled. this also applies to the timer output compare1 flags and interrupts. 8-bit timer/counter2 figure 34 shows the block diagram for timer/counter2. figure 34. timer/counter2 block diagram the 8-bit timer/counter2 can select clock source from pck2 or prescaled pck2. it can also be stopped as described in the specification for the timer/counter control register (tccr2). the different status flags (overflow and compare match) are found in the timer/counter interrupt flag register (tifr). control signals are found in the 10top h 1 1 $0000 h 11top l table 16. pwm outputs ocr1x = $0000 or top com1x1 com1x0 ocr1x output oc1x 8-bit data bus 8-bit asynch t/c2 data bus asynch. status register (assr) timer int. flag register (tifr) timer/counter2 (tcnt2) synch unit 8-bit comparator output compare register2 (ocr2) timer int. mask register (timsk) 0 0 0 7 7 7 t/c clk source up/down t/c clear control logic tov0 tov1 ocf1b ocf1a icf1 tov2 ocf2 ocf2 tov2 toie0 toie1 ocie1a ocie1b ticie1 toie2 ocie2 ocr2ub tc2ub icr2ub tosc1 ck pck2 t/c2 over- flow irq t/c2 compare match irq t/c2 control register (tccr2) cs22 com21 pwm2 as2 cs21 com20 cs20 ctc2 ck 43 at90s/ls8535 1041h ? 11/01 timer/counter control register (tccr2). the interrupt enable/disable settings are found in the timer/counter interrupt mask register (timsk). this module features a high-resolution and a high-accuracy usage with the lower pres- caling opportunities. similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. the timer/counter supports an output compare function using the output compare register (ocr2) as the data source to be compared to the timer/counter contents.the output compare function includes optional clearing of the counter on compare match and action on the output compare pin, pd7(oc2), on compare match. writing to portd7 does not set the oc2 value to a predetermined value. timer/counter2 can also be used as an 8-bit pulse width modulator. in this mode, timer/counter2 and the output compare register serve as a glitch-free, stand-alone pwm with centered pulses. refer to page 45 for a detailed description of this function. timer/counter2 control register ? tccr2 bit 7 ? res: reserved bit this bit is a reserved bit in the at90s8535 and always reads as zero. bit 6 ? pwm2: pulse width modulator enable when set (one), this bit enables pwm mode for timer/counter2. this mode is described on page 45. bits 5, 4 ? com21, com20: compare output mode, bits 1 and 0 the com21 and com20 control bits determine any output pin action following a com- pare match in timer/counter2. output pin actions affect pin pd7(oc2). this is an alternative function to an i/o port and the corresponding direction control bit must be set (one) to control an output pin. the control configuration is shown in table 17. note: in pwm mode, these bits have a different function. refer to table 19 for a detailed description. bit 3 ? ctc2: clear timer/counter on compare match when the ctc2 control bit is set (one), timer/counter2 is reset to $00 in the cpu clock cycle after a compare match. if the control bit is cleared, timer/counter2 continues counting and is unaffected by a compare match. since the compare match is detected in the cpu clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. when a prescaling of 1 is used and the compare2 register is set to c, the timer will count as follows if ctc2 is set: ... | c-2 | c-1 | c | 0 | 1 |... bit 76543210 $25 ($45) ? pwm2 com21 com20 ctc2 cs22 cs21 cs20 tccr2 read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 17. compare mode select com21 com20 description 0 0 timer/counter disconnected from output pin oc2 0 1 toggle the oc2 output line. 1 0 clear the oc2 output line (to zero). 1 1 set the oc2 output line (to one). 44 at90s/ls8535 1041h ? 11/01 when the prescaler is set to divide by 8, the timer will count like this: ... | c-2, c-2, c-2, c-2, c-2, c-2, c-2, c-2 | c-1, c-1, c-1, c-1, c-1, c-1, c-1, c-1 | c, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1,... in pwm mode, this bit has no effect. bits 2, 1, 0 ? cs22, cs21, cs20: clock select bits 2, 1 and 0 the clock select bits 2,1 and 0 define the prescaling source of timer/counter2. the stop condition provides a timer enable/disable function. the prescaled ck modes are scaled directly from the ck oscillator clock. timer/counter2 ? tcnt2 this 8-bit register contains the value of timer/counter2. timer/counter2 is realized as an up or up/down (in pwm mode) counter with read and write access. if the timer/counter2 is written to and a clock source is selected, it contin- ues counting in the timer clock cycle following the write operation. timer/counter2 output compare register ? ocr2 the output compare register is an 8-bit read/write register. the timer/counter output compare register contains the data to be continuously com- pared with timer/counter2. actions on compare matches are specified in tccr2. a compare match only occurs if timer/counter2 counts to the ocr2 value. a software write that sets tcnt2 and ocr2 to the same value does not generate a compare match. a compare match will set the compare interrupt flag in the cpu clock cycle following the compare event. table 18. timer/counter2 prescale select cs22 cs21 cs20 description 0 0 0 timer/counter2 is stopped. 001pck2 010pck2/ 8 011pck2/ 32 100pck2/ 64 1 0 1 pck2/128 1 1 0 pck2/256 1 1 1 pck2/1024 bit 76543210 $24 ($44) msb lsb tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $23 ($43) msb lsb ocr2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 45 at90s/ls8535 1041h ? 11/01 timer/counter2 in pwm mode when the pwm mode is selected, timer/counter2 and the output compare register (ocr2) form an 8-bit, free-running, glitch-free and phase correct pwm with outputs on the pd7(oc2) pin. timer/counter2 acts as an up/down counter, counting up from $00 to $ff, where it turns and counts down again to zero before the cycle is repeated. when the counter value matches the contents of the output compare register, the pd7(oc2) pin is set or cleared according to the settings of the com21/com20 bits in the timer/counter2 control register (tccr2). refer to table 19 for details. note that in pwm mode, the output compare register is transferred to a temporary location when written. the value is latched when the timer/counter reaches $ff. this prevents the occurrence of odd-length pwm pulses (glitches) in the event of an unsyn- chronized ocr2 write. see figure 35 for an example. figure 35. effects of unsynchronized ocr latching during the time between the write and the latch operation, a read from ocr2 will read the contents of the temporary location. this means that the most recently written value always will read out of ocr2. when the ocr register (not the temporary register) is updated to $00 or $ff, the pwm output changes to low or high immediately according to the settings of com21/com20. this is shown in table 20. table 19. compare mode select in pwm mode com21 com20 effect on compare pin 0 0 not connected 0 1 not connected 1 0 cleared on compare match, up-counting. set on compare match, down- counting (non-inverted pwm). 1 1 cleared on compare match, down-counting time-out. set on compare match, up-counting (inverted pwm). table 20. pwm outputs ocr2 = $00 or $ff com21 com20 ocr2 output pwm2 10$00 l counter value compare valu e pwm output synchronized ocr latch counter value compare valu e pwm output unsynchronized ocr latch glitch compare value changes compare value changes 46 at90s/ls8535 1041h ? 11/01 in pwm mode, the timer overflow flag (tov2) is set when the counter advances from $00. timer overflow interrupt2 operates exactly as in normal timer/counter mode, i.e., it is executed when tov2 is set, provided that timer overflow interrupt and global inter- rupts are enabled. this also applies to the timer output compare flag and interrupt. the frequency of the pwm will be timer clock frequency divided by 510. asynchronous status register ? assr bit 7..4 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read as zero. bit 3 ? as2: asynchronous timer/counter2 when as2 is set (one), timer/counter2 is clocked from the tosc1 pin. pins pc6 and pc7 become connected to a crystal oscillator and cannot be used as general i/o pins. when cleared (zero), timer/counter2 is clocked from the internal system clock, ck. when the value of this bit is changed, the contents of tcnt2, ocr2 and tccr2 might get corrupted. bit 2 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set (one). when tcnt2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. a logical ? 0 ? in this bit indicates that tcnt2 is ready to be updated with a new value. bit 1 ? ocr2ub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2 is written, this bit becomes set (one). when ocr2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. a logical ? 0 ? in this bit indicates that ocr2 is ready to be updated with a new value. bit 0 ? tcr2ub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2 is written, this bit becomes set (one). when tccr2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. a logical ? 0 ? in this bit indicates that tccr2 is ready to be updated with a new value. if a write is performed to any of the three timer/counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional inter- rupt to occur. the mechanisms for reading tcnt2, ocr2 and tccr2 are different. when reading tcnt2, the actual timer value is read. when reading ocr2 or tccr2, the value in the temporary storage register is read. 10$ff h 11$00 h 11$ff l table 20. pwm outputs ocr2 = $00 or $ff com21 com20 ocr2 output pwm2 bit 76543 2 1 0 $22 ($22) ???? as2 tcn2ub ocr2ub tcr2ub assr read/write r r r r r/w r r r initial value 0 0 0 0 0 0 0 0 47 at90s/ls8535 1041h ? 11/01 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. warning: when switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2 and tccr2 might get corrupted. a safe procedure for switching clock source is: 1. disable the timer/counter2 interrupts ocie2 and toie2. 2. select clock source by setting as2 as appropriate. 3. write new values to tcnt2, ocr2 and tccr2. 4. to switch to asynchronous operation: wait for tcn2ub, ocr2ub and tcr2ub. 5. clear the timer/counter2 interrupt flags. 6. clear the tov2 and ocf2 flags in tifr. 7. enable interrupts, if needed. when writing to one of the registers tcnt2, ocr2 or tccr2, the value is transferred to a temporary register and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to their destination. each of the three mentioned registers have their individual temporary register. for example, writing to tcnt2 does not disturb an ocr2 write in progress. to detect that a transfer to the destination register has taken place, an asynchronous status register (assr) has been implemented. when entering a power save mode after having written to tcnt2, ocr2 or tccr2, the user must wait until the written register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will go to sleep before the changes have had any effect. this is extremely important if the output compare2 interrupt is used to wake up the device; output compare is disabled during write to ocr2 or tcnt2. if the write cycle is not finished (i.e., the user goes to sleep before the ocr2ub bit returns to zero), the device will never get a compare match and the mcu will not wake up. if timer/counter2 is used to wake up the device from power save mode, precautions must be taken if the user wants to re-enter power save mode: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake up and re-entering power save mode is less than one tosc1 cycle, the interrupt will not occur and the device will fail to wake up. if the user is in doubt whether the time before re-entering power save is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: 1. write a value to tccr2, tcnt2 or ocr2. 2. wait until the corresponding update busy flag in assr returns to zero. 3. enter power save mode. when the asynchronous operation is selected, the 32 khz oscillator for timer/counter2 is always running, except in power-down mode. after a power-up reset or wake-up from power-down, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down. the content of all timer/counter2 registers must be considered lost after a wake-up from power-down due to the unstable clock signal upon start-up, regardless of whether the oscillator is in use or a clock signal is applied to the tosc pin. description of wake-up from power save mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake-up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at 48 at90s/ls8535 1041h ? 11/01 least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. the timer is therefore advanced by at least 1 before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 49 at90s/ls8535 1041h ? 11/01 watchdog timer the watchdog timer is clocked from a separate on-chip oscillator. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 21. see characterization data for typical values at other v cc levels. the wdr (watchdog reset) instruction resets the watchdog timer. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the at90s8535 resets and executes from the reset vector. for timing details on the watchdog reset, refer to page 22. to prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 36. watchdog timer watchdog timer control register ? wdtcr bits 7..5 ? res: reserved bits these bits are reserved bits in the at90s8535 and will always read as zero. bit 4 ? wdtoe: watchdog turn-off enable this bit must be set (one) when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, hardware will clear this bit to zero after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. bit 3 ? wde: watchdog enable when the wde is set (one) the watchdog timer is enabled and if the wde is cleared (zero) the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set (one). to disable an enabled watchdog timer, the following procedure must be followed: 1 mhz at v cc = 5v 350 khz at v cc = 3v oscillator bit 76543210 $21 ($41) ??? wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 50 at90s/ls8535 1041h ? 11/01 1. in the same operation, write a logical ? 1 ? to wdtoe and wde. a logical ? 1 ? must be written to wde even though it is set to ? 1 ? before the disable operation starts. 2. within the next four clock cycles, write a logical ? 0 ? to wde. this disables the watchdog. bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1 and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 21. note: the frequency of the watchdog oscillator is voltage-dependent as shown in the electrical characteristics section. the wdr (watchdog reset) instruction should always be executed before the watchdog timer is enabled. this ensures that the reset period will be in accordance with the watchdog timer prescale settings. if the watchdog timer is enabled without reset, the watchdog timer may not start to count from zero. to avoid unintentional mcu resets, the watchdog timer should be disabled or reset before changing the watchdog timer prescale select. table 21. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 47 ms 15 ms 0 0 1 32k cycles 94 ms 30 ms 0 1 0 64k cycles 0.19 s 60 ms 0 1 1 128k cycles 0.38 s 0.12 s 1 0 0 256k cycles 0.75 s 0.24 s 1 0 1 512k cycles 1.5 s 0.49 s 1 1 0 1,024k cycles 3.0 s 0.97 s 1 1 1 2,048k cycles 6.0 s 1.9 s 51 at90s/ls8535 1041h ? 11/01 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time is in the range of 2.5 - 4 ms, depending on the v cc voltages. a self-timing function lets the user software detect when the next byte can be written. a special eeprom ready interrupt can be set to trigger when the eeprom is ready to accept new data. in order to prevent unintentional eeprom writes, a specific write procedure must be fol- lowed. refer to the description of the eeprom control register for details on this. when the eeprom is read, the cpu is halted for four clock cycles before the next instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. eeprom address register ? eearh and eearl the eeprom address registers (eearh and eearl) specify the eeprom address in the 512-byte eeprom space. the eeprom data bytes are addressed linearly between 0 and 511. eeprom data register ? eedr bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read opera- tion, the eedr contains the data read out from the eeprom at the address given by eear. eeprom control register ? eecr bit 7..4 ? res: reserved bits these bits are reserved bits in the at90s8535 and will always read as zero. bit 3 ? eerie: eeprom ready interrupt enable when the i-bit in sreg and eerie are set (one), the eeprom ready interrupt is enabled. when cleared (zero), the interrupt is disabled. the eeprom ready interrupt generates a constant interrupt when eewe is cleared (zero). bit 151413121110 9 8 $1f ($3f) ??????? eear8 eearh $1e ($3e) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543210 read/writerrrrrrrr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 x xxxxxxxx bit 76543210 $1d ($3d) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $1c ($3c) ???? eerie eemwe eewe eere eecr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 52 at90s/ls8535 1041h ? 11/01 bit 2 ? eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to ? 1 ? causes the eeprom to be written. when eemwe is set (one), setting eewe will write data to the eeprom at the selected address. if eemwe is zero, setting eewe will have no effect. when eemwe has been set (one) by software, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for a eeprom write procedure. bit 1 ? eewe: eeprom write enable the eeprom write enable signal (eewe) is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be set to write the value into the eeprom. the eemwe bit must be set when the logical ? 1 ? is written to eewe, oth- erwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 2 and 3 is unessential): 1. wait until eewe becomes zero. 2. write new eeprom address to eearl and eearh (optional). 3. write new eeprom data to eedr (optional). 4. write a logical ? 1 ? to the eemwe bit in eecr (to be able to write a logical ? 1 ? to the eemwe bit, the eewe bit must be written to ? 0 ? in the same cycle). 5. within four clock cycles after setting eemwe, write a logical ? 1 ? to eewe. caution: an interrupt between step 4 and step 5 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom access, the eear and eedr registers will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during the four last steps to avoid these problems. when the write access time (typically 2.5 ms at v cc = 5v or 4 ms at v cc = 2.7v) has elapsed, the eewe bit is cleared (zero) by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two clock cycles before the next instruction is executed. bit 0 ? eere: eeprom read enable the eeprom read enable signal (eere) is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be set. when the eere bit is cleared (zero) by hardware, requested data is found in the eedr register. the eeprom read access takes one instruction and there is no need to poll the eere bit. when eere has been set, the cpu is halted for four clock cycles before the next instruction is executed. the user should poll the eewe bit before starting the read operation. if a write operation is in progress when new data or address is written to the eeprom i/o registers, the write operation will be interrupted and the result is undefined. 53 at90s/ls8535 1041h ? 11/01 prevent eeprom corruption during periods of low v cc , the eeprom data can be corrupted because the supply volt- age is too low for the cpu and the eeprom to operate properly. these issues are the same as for board level systems using the eeprom and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the eeprom requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. eeprom data corruption can easily be avoided by following these design recommen- dations (one is sufficient): 1. keep the avr reset active (low) during periods of insufficient power supply voltage. this is best done by an external low v cc reset protection circuit, often referred to as a brown-out detector (bod). please refer to application note avr 180 for design considerations regarding power-on reset and low-voltage detection. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute instructions, effec- tively protecting the eeprom registers from unintentional writes. 3. store constants in flash memory if the ability to change memory contents from software is not required. flash memory cannot be updated by the cpu and will not be subject to corruption. 54 at90s/ls8535 1041h ? 11/01 serial peripheral interface ? spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at90s8535 and peripheral devices or between several avr devices. the at90s8535 spi features include the following: full-duplex, 3-wire synchronous data transfer master or slave operation lsb first or msb first data transfer four programmable bit rates end-of-transmission interrupt flag write collision flag protection wake-up from idle mode figure 37. spi block diagram the interconnection between master and slave cpus with spi is shown in figure 38. the pb7(sck) pin is the clock output in the master mode and is the clock input in the slave mode. writing to the spi data register of the master cpu starts the spi clock generator and the data written shifts out of the pb5(mosi) pin and into the pb5(mosi) pin of the slave cpu. after shifting one byte, the spi clock generator stops, setting the end-of-transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr regis- ter is set, an interrupt is requested. the slave select input, pb4(ss), is set low to select an individual slave spi device. the two shift registers in the master and the slave can be considered as one distributed 16-bit circular shift register. this is shown in figure 38. when data is shifted from the master to the slave, data is also shifted in the opposite direction, simultaneously. during one shift cycle, data in the master and the slave is interchanged. 55 at90s/ls8535 1041h ? 11/01 figure 38. spi master-slave interconnection the system is single-buffered in the transmit direction and double-buffered in the receive direction. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received byte must be read from the spi data register before the next byte has been completely shifted in. otherwise, the first byte is lost. when the spi is enabled, the data direction of the mosi, miso, sck and ss pins is overridden according to table 22. note: see ? alternate functions of port b ? on page 79 f or a detailed description of how to define the direction of the user-defined spi pins. table 22. spi pin overrides pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input msb master lsb 8 bit shift register msb master lsb 8 bit shift register miso mosi spi clock generator sck ss miso mosi sck ss v cc 56 at90s/ls8535 1041h ? 11/01 ss pin functionality when the spi is configured as a master (mstr in spcr is set), the user can determine the direction of the ss pin. if ss is configured as an output, the pin is a general output pin, which does not affect the spi system. if ss is configured as an input, it must be held high to ensure master spi operation. if the ss pin is driven low by peripheral circuitry when the spi is configured as master with the ss pin defined as an input, the spi sys- tem interprets this as another master selecting the spi as a slave and starting to send data to it. to avoid bus contention, the spi system takes the following actions: 1. the mstr bit in spcr is cleared and the spi system becomes a slave. as a result of the spi becoming a slave, the mosi and sck pins become inputs. 2. the spif flag in spsr is set and if the spi interrupt is enabled and the i-bit in sreg are set, the interrupt routine will be executed. thus, when interrupt-driven spi transmission is used in master mode and there exists a possibility that ss is driven low, the interrupt should always check that the mstr bit is still set. once the mstr bit has been cleared by a slave select, it must be set by the user to re-enable the spi master mode. when the spi is configured as a slave, the ss pin is always input. when ss is held low, the spi is activated and miso becomes an output if configured so by the user. all other pins are inputs. when ss is driven high, all pins are inputs and the spi is passive, which means that it will not receive incoming data. note that the spi logic will be reset once the ss pin is brought high. if the ss pin is brought high during a transmission, the spi will stop sending and receiving immediately and both data received and data sent must be considered as lost. data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 39 and figure 40. figure 39. spi transfer format with cpha = 0 and dord = 0 sample *not defined but normally msb of character just received. sck cycle# (for reference) sck (cpol=0) sck (cpol=1) mosi (from master) miso (from slave) ss (to slave) 1234 56 78 msb 1 2 3 4 5 6 lsb msb 1 2 3 4 5 6 lsb * 57 at90s/ls8535 1041h ? 11/01 figure 40. spi transfer format with cpha = 1 and dord = 0 spi control register ? spcr bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and the global interrupts are enabled. bit 6 ? spe: spi enable when the spe bit is set (one), the spi is enabled. this bit must be set to enable any spi operations. bit 5 ? dord: data order when the dord bit is set (one), the lsb of the data word is transmitted first. when the dord bit is cleared (zero), the msb of the data word is transmitted first. bit 4 ? mstr: master/slave select this bit selects master spi mode when set (one) and slave spi mode when cleared (zero). if ss is configured as an input and is driven low while mstr is set, mstr will be cleared and spif in spsr will become set. the user will then have to set mstr to re- enable spi master mode. bit 3 ? cpol: clock polarity when this bit is set (one), sck is high when idle. when cpol is cleared (zero), sck is low when idle. refer to figure 39. and figure 40. for additional information. bit 2 ? cpha: clock phase refer to figure 40 or figure 41 for the functionality of this bit. bit 76543210 $0d ($2d) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 58 at90s/ls8535 1041h ? 11/01 bits 1,0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f cl is shown in table 23. spi status register ? spsr bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif bit is set (one) and an interrupt is gener- ated if spie in spcr is set (one) and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alter- natively, the spif bit is cleared by first reading the spi status register with spif set (one), then accessing the spi data register (spdr). bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared (zero) by first reading the spi status reg- ister with wcol set (one) and then accessing the spi data register. bit 5..0 ? res: reserved bits these bits are reserved bits in the at90s8535 and will always read as zero. the spi interface on the at90s8535 is also used for program memory and eeprom downloading or uploading. see page 99 for serial programming and verification. spi data register ? spdr the spi data register is a read/write register used for data transfer between the regis- ter file and the spi shift register. writing to the register initiates data transmission. reading the register causes the shift register receive buffer to be read. table 23. relationship between sck and the oscillator frequency spr1 spr0 sck frequency 00 f cl /4 01 f cl /16 10 f cl /64 11 f cl /128 bit 76543210 $0e ($2e) spif wcol ?????? spsr read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 $0f ($2f) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined 59 at90s/ls8535 1041h ? 11/01 uart the at90s8535 features a full duplex (separate receive and transmit registers) univer- sal asynchronous receiver and transmitter (uart). the main features are: baud rate generator that can generate a large number of baud rates (bps) high baud rates at low xtal frequencies 8 or 9 bits data noise filtering overrun detection framing error detection false start bit detection three separate interrupts on tx complete, tx data register empty and rx complete buffered transmit and receive data transmission a block schematic of the uart transmitter is shown in figure 41. figure 41. uart transmitter data transmission is initiated by writing the data to be transmitted to the uart i/o data register, udr. data is transferred from udr to the transmit shift register when: a new character is written to udr after the stop bit from the previous character has been shifted out. the shift register is loaded immediately. a new character is written to udr before the stop bit from the previous character has been shifted out. the shift register is loaded when the stop bit of the character currently being transmitted is shifted out. if the 10(11)-bit transmitter shift register is empty, data is transferred from udr to the shift register. the udre (uart data register empty) bit in the uart status register, usr, is set. when this bit is set (one), the uart is ready to receive the next character. at the same time as the data is transferred from udr to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). if 9-bit data word 60 at90s/ls8535 1041h ? 11/01 is selected (the chr9 bit in the uart control register, ucr is set), the txb8 bit in ucr is transferred to bit 9 in the transmit shift register. on the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the txd pin. then follows the data, lsb first. when the stop bit has been shifted out, the shift register is loaded if any new data has been written to the udr dur- ing the transmission. during loading, udre is set. if there is no new data in the udr register to send when the stop bit is shifted out, the udre flag will remain set until udr is written again. when no new data has been written and the stop bit has been present on txd for one bit length, the tx complete flag (txc) in usr is set. the txen bit in ucr enables the uart transmitter when set (one). when this bit is cleared (zero), the pd1 pin can be used for general i/o. when txen is set, the uart transmitter will be connected to pd1, which is forced to be an output pin regardless of the setting of the ddd1 bit in ddrd. data reception figure 42 shows a block diagram of the uart receiver. figure 42. uart receiver the receiver front-end logic samples the signal on the rxd pin at a frequency 16 times the baud rate. while the line is idle, one single sample of logical ? 0 ? will be interpreted as the falling edge of a start bit and the start bit detection sequence is initiated. let sample 61 at90s/ls8535 1041h ? 11/01 1 denote the first zero-sample. following the 1-to-0 transition, the receiver samples the rxd pin at samples 8, 9 and 10. if two or more of these three samples are found to be logical ? 1 ? s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. if however, a valid start bit is detected, sampling of the data bits following the start bit is performed. these bits are also sampled at samples 8, 9 and 10. the logical value found in at least two of the three samples is taken as the bit value. all bits are shifted into the transmitter shift register as they are sampled. sampling of an incoming character is shown in figure 43. figure 43. sampling received data when the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. if two or more samples are logical ? 0 ? s, the framing error (fe) flag in the uart status register (usr) is set. before reading the udr register, the user should always check the fe bit to detect framing errors. whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to udr and the rxc flag in usr is set. udr is in fact two physically separate registers, one for transmitted data and one for received data. when udr is read, the receive data register is accessed and when udr is written, the transmit data register is accessed. if 9-bit data word is selected (the chr9 bit in the uart con- trol register, ucr is set), the rxb8 bit in ucr is loaded with bit 9 in the transmit shift register when data is transferred to udr. if, after having received a character, the udr register has not been read since the last receive, the overrun (or) flag in ucr is set. this means that the last data byte shifted into the shift register could not be transferred to udr and has been lost. the or bit is buffered and is updated when the valid data byte in udr is read. thus, the user should always check the or bit after reading the udr register in order to detect any overruns if the baud rate is high or cpu load is high. when the rxen bit in the ucr register is cleared (zero), the receiver is disabled. this means that the pd0 pin can be used as a general i/o pin. when rxen is set, the uart receiver will be connected to pd0, which is forced to be an input pin regardless of the setting of the ddd0 bit in ddrd. when pd0 is forced to input by the uart, the portd0 bit can still be used to control the pull-up resistor on the pin. when the chr9 bit in the ucr register is set, transmitted and received characters are 9 bits long, plus start and stop bits. the ninth data bit to be transmitted is the txb8 bit in ucr register. this bit must be set to the wanted value before a transmission is initiated by writing to the udr register. the ninth data bit received is the rxb8 bit in the ucr register. 62 at90s/ls8535 1041h ? 11/01 uart control uart i/o data register ? udr the udr register is actually two physically separate registers sharing the same i/o address. when writing to the register, the uart transmit data register is written. when reading from udr, the uart receive data register is read. uart status register ? usr the usr register is a read-only register providing information on the uart status. bit 7 ? rxc: uart receive complete this bit is set (one) when a received character is transferred from the receiver shift reg- ister to udr. the bit is set regardless of any detected framing errors. when the rxcie bit in ucr is set, the uart receive complete interrupt will be executed when rxc is set (one). rxc is cleared by reading udr. when interrupt-driven data reception is used, the uart receive complete interrupt routine must read udr in order to clear rxc, otherwise a new interrupt will occur once the interrupt routine terminates. bit 6 ? txc: uart transmit complete this bit is set (one) when the entire character (including the stop bit) in the transmit shift register has been shifted out and no new data has been written to udr. this flag is especially useful in half-duplex communications interfaces, where a transmitting appli- cation must enter receive mode and free the communications bus immediately after completing the transmission. when the txcie bit in ucr is set, setting of txc causes the uart transmit complete interrupt to be executed. txc is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the txc bit is cleared (zero) by writing a logical ? 1 ? to the bit. bit 5 ? udre: uart data register empty this bit is set (one) when a character written to udr is transferred to the transmit shift register. setting of this bit indicates that the transmitter is ready to receive a new charac- ter for transmission. when the udrie bit in ucr is set, the uart transmit complete interrupt to be exe- cuted as long as udre is set. udre is cleared by writing udr. when interrupt-driven data transmission is used, the uart data register empty interrupt routine must write udr in order to clear udre, otherwise a new interrupt will occur once the interrupt rou- tine terminates. udre is set (one) during reset to indicate that the transmitter is ready. bit 4 ? fe: framing error this bit is set if a framing error condition is detected, i.e., when the stop bit of an incom- ing character is zero. bit 76543210 $0c ($2c) msb lsb udr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $0b ($2b) rxc txc udre fe or ??? usr read/write r r/w r r r r r r initial value 0 0 1 0 0 0 0 0 63 at90s/ls8535 1041h ? 11/01 the fe bit is cleared when the stop bit of received data is one. bit 3 ? or: overrun this bit is set if an overrun condition is detected, i.e., when a character already present in the udr register is not read before the next character has been shifted into the receiver shift register. the or bit is buffered, which means that it will be set once the valid data still in udr is read. the or bit is cleared (zero) when data is received and transferred to udr. bits 2..0 ? res: reserved bits these bits are reserved bits in the at90s8535 and will always read as zero. uart control register ? ucr bit 7 ? rxcie: rx complete interrupt enable when this bit is set (one), a setting of the rxc bit in usr will cause the receive com- plete interrupt routine to be executed provided that global interrupts are enabled. bit 6 ? txcie: tx complete interrupt enable when this bit is set (one), a setting of the txc bit in usr will cause the transmit com- plete interrupt routine to be executed provided that global interrupts are enabled. bit 5 ? udrie: uart data register empty interrupt enable when this bit is set (one), a setting of the udre bit in usr will cause the uart data register empty interrupt routine to be executed provided that global interrupts are enabled. bit 4 ? rxen: receiver enable this bit enables the uart receiver when set (one). when the receiver is disabled, the rxc, or and fe status flags cannot become set. if these flags are set, turning off rxen does not cause them to be cleared. bit 3 ? txen: transmitter enable this bit enables the uart transmitter when set (one). when disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in udr has been completely transmitted. bit 2 ? chr9: 9 bit characters when this bit is set (one), transmitted and received characters are 9 bits long, plus start and stop bits. the ninth bit is read and written by using the rxb8 and txb8 bits in ucr, respectively. the ninth data bit can be used as an extra stop bit or a parity bit. bit 1 ? rxb8: receive data bit 8 when chr9 is set (one), rxb8 is the ninth data bit of the received character. bit 0 ? txb8: transmit data bit 8 when chr9 is set (one), txb8 is the ninth data bit in the character to be transmitted. bit 76543210 $0a ($2a) rxcie txcie udrie rxen txen chr9 rxb8 txb8 ucr read/write r/w r/w r/w r/w r/w r/w r w initial value 0 0 0 0 0 0 1 0 64 at90s/ls8535 1041h ? 11/01 baud rate generator the baud rate generator is a frequency divider which generates baud rates according to the following equation: baud = baud rate f ck = crystal clock frequency ubrr = contents of the uart baud rate register, ubrr (0 - 255) for standard crystal frequencies, the most commonly used baud rates can be generated by using the ubrr settings in table 24. ubrr values that yield an actual baud rate dif- fering less than 2% from the target baud rate are boldface in the table. however, using baud rates that have more than 1% error is not recommended. high error ratings give less noise resistance. table 24. ubrr settings at various crystal frequencies (examples) note: maximum baud rate to each frequency. baud f ck 16(ubrr 1 ) + ------------------------------------- - = baud rate 1mhz %error 1.8432 mhz %error 2mhz %error 2.4576 mhz %error 2400 ubrr= 25 0.2 ubrr= 47 0.0 ubrr= 51 0.2 ubrr= 63 0.0 4800 ubrr= 12 0.2 ubrr= 23 0.0 ubrr= 25 0.2 ubrr= 31 0.0 9600 ubrr= 6 7.5 ubrr= 11 0.0 ubrr= 12 0.2 ubrr= 15 0.0 14400 ubrr= 3 7.8 ubrr= 70.0 ubrr= 8 3.7 ubrr= 10 3.1 19200 ubrr= 2 7.8 ubrr= 50.0 ubrr= 6 7.5 ubrr= 70.0 28800 ubrr= 1 7.8 ubrr= 30.0 ubrr= 3 7.8 ubrr= 4 6.3 38400 ubrr= 1 22.9 ubrr= 20.0 ubrr= 2 7.8 ubrr= 30.0 57600 ubrr= 0 7.8 ubrr= 10.0 ubrr= 1 7.8 ubrr= 2 12.5 76800 ubrr= 0 22.9 ubrr= 1 33.3 ubrr= 1 22.9 ubrr= 10.0 115200 ubrr= 0 84.3 ubrr= 00.0 ubrr= 0 7.8 ubrr= 0 25.0 baud rate 3.2768 mhz %error 3.6864 mhz %error 4mhz %error 4.608 mhz %error 2400 ubrr= 84 0.4 ubrr= 95 0.0 ubrr= 103 0.2 ubrr= 119 0.0 4800 ubrr= 42 0.8 ubrr= 47 0.0 ubrr= 51 0.2 ubrr= 59 0.0 9600 ubrr= 20 1.6 ubrr= 23 0.0 ubrr= 25 0.2 ubrr= 29 0.0 14400 ubrr= 13 1.6 ubrr= 15 0.0 ubrr= 16 2.1 ubrr= 19 0.0 19200 ubrr= 10 3.1 ubrr= 11 0.0 ubrr= 12 0.2 ubrr= 14 0.0 28800 ubrr= 61.6 ubrr= 70.0 ubrr= 8 3.7 ubrr= 90.0 38400 ubrr= 4 6.3 ubrr= 50.0 ubrr= 6 7.5 ubrr= 7 6.7 57600 ubrr= 3 12.5 ubrr= 30.0 ubrr= 3 7.8 ubrr= 40.0 76800 ubrr= 2 12.5 ubrr= 20.0 ubrr= 2 7.8 ubrr= 3 6.7 115200 ubrr= 1 12.5 ubrr= 10.0 ubrr= 1 7.8 ubrr= 2 20.0 baud rate 7.3728 mhz %error 8mhz %error 9.216 mhz %error 11.059 mhz %error 2400 ubrr= 191 0.0 ubrr= 207 0.2 ubrr= 239 0.0 ubrr= 287 - 4800 ubrr= 95 0.0 ubrr= 103 0.2 ubrr= 119 0.0 ubrr= 143 0.0 9600 ubrr= 47 0.0 ubrr= 51 0.2 ubrr= 59 0.0 ubrr= 71 0.0 14400 ubrr= 31 0.0 ubrr= 34 0.8 ubrr= 39 0.0 ubrr= 47 0.0 19200 ubrr= 23 0.0 ubrr= 25 0.2 ubrr= 29 0.0 ubrr= 35 0.0 28800 ubrr= 15 0.0 ubrr= 16 2.1 ubrr= 19 0.0 ubrr= 23 0.0 38400 ubrr= 11 0.0 ubrr= 12 0.2 ubrr= 14 0.0 ubrr= 17 0.0 57600 ubrr= 70.0 ubrr= 8 3.7 ubrr= 90.0 ubrr= 11 0.0 76800 ubrr= 50.0 ubrr= 6 7.5 ubrr= 7 6.7 ubrr= 80.0 115200 ubrr= 30.0 ubrr= 3 7.8 ubrr= 40.0 ubrr= 50.0 65 at90s/ls8535 1041h ? 11/01 uart baud rate register ? ubrr the ubrr register is an 8-bit read/write register that specifies the uart baud rate according to the equation on the previous page. bit 76543210 $09 ($29) msb lsb ubrr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 66 at90s/ls8535 1041h ? 11/01 analog comparator the analog comparator compares the input values on the positive input pb2 (ain0) and negative input pb3 (ain1). when the voltage on the positive input pb2 (ain0) is higher than the voltage on the negative input pb3 (ain1), the analog comparator output (aco) is set (one). the comparator ? s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on compar- ator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 44 . figure 44. analog comparator block diagram analog comparator control and status register ? acsr bit 7 ? acd: analog comparator disable when this bit is set (one), the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. bit 6 ? res: reserved bit this bit is a reserved bit in the at90s8535 and will always read as zero. bit 5 ? aco: analog comparator output aco is directly connected to the comparator output. bit 4 ? aci: analog comparator interrupt flag this bit is set (one) when a comparator output event triggers the interrupt mode defined by aci1 and aci0. the analog comparator interrupt routine is executed if the acie bit is set (one) and the i-bit in sreg is set (one). aci is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logical ? 1 ? to the flag. bit 3 ? acie: analog comparator interrupt enable when the acie bit is set (one) and the i-bit in the status register is set (one), the ana- log comparator interrupt is activated. when cleared (zero), the interrupt is disabled. bit 76543210 $08 ($28) acd ? aco aci acie acic acis1 acis0 acsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 67 at90s/ls8535 1041h ? 11/01 bit 2 ? acic: analog comparator input capture enable when set (one), this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when cleared (zero), no connection between the analog comparator and the input capture function is given. to make the comparator trigger the timer/counter1 input capture interrupt, the ticie1 bit in the timer interrupt mask register (timsk) must be set (one). bits 1,0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events trigger the analog comparator interrupt. the different settings are shown in table 25. note: when changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. caution : using the sbi or cbi instruction on bits other than aci in this register will write a ? 1 ? back into aci if it is read as set, thus clearing the flag. table 25. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge 68 at90s/ls8535 1041h ? 11/01 analog-to-digital converter feature list 10-bit resolution 0.5 lsb integral non-linearity 2 lsb absolute accuracy 65 - 260 s conversion time up to 15 ksps at maximum resolution 8 multiplexed input channels rail-to-rail input range free running or single conversion mode interrupt on adc conversion complete sleep mode noise canceler the at90s8535 features a 10-bit successive approximation adc. the adc is con- nected to an 8-channel analog multiplexer that allows each pin of port a to be used as an input for the adc. the adc contains a sample and hold amplifier that ensures that the input voltage to the adc is held at a constant level during conversion. a block dia- gram of the adc is shown in figure 45. the adc has two separate analog supply voltage pins, avcc and agnd. agnd must be connected to gnd and the voltage on av cc must not differ more than 0.3v from v cc . see ? adc noise canceling techniques ? on page 74 on how to connect these pins. an external reference voltage must be applied to the aref pin. this voltage must be in the range 2v - av cc . figure 45. analog-to-digital converter block schematic adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl & status register (adcsr) adc data register (adch/adcl) mux2 adie adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 8- channel mux conversion logic 10-bit dac + - sample & hold comparator adc9..0 prescaler aref adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 69 at90s/ls8535 1041h ? 11/01 operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents agnd and the maximum value repre- sents the voltage on the aref pin minus one lsb. the analog input channel is selected by writing to the mux bits in admux. any of the eight adc input pins adc7..0 can be selected as single-ended inputs to the adc. the adc can operate in two modes ? single conversion and free running. in single conversion mode, each conversion will have to be initiated by the user. in free running mode, the adc is constantly sampling and updating the adc data register. the adfr bit in adcsr selects between the two available modes. the adc is enabled by setting the adc enable bit, aden in adcsr. input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power-saving sleep modes. a conversion is started by writing a logical ? 1 ? to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be set to zero by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conversion before performing the channel change. the adc generates a 10-bit result, which is presented in the adc data register, adch and adcl. when reading data, adcl must be read first, then adch, to ensure that the content of the data register belongs to the same conversion. once adcl is read, adc access to data register is blocked. this means that if adcl has been read and a con- version completes before adch is read, neither register is updated and the result from the conversion is lost. then adch is read, adc access to the adch and adcl register is re-enabled. the adc has its own interrupt that can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. prescaling figure 46. adc prescaler the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to achieve maximum resolution. if a resolution of lower than 10 bits is required, the input clock frequency to the adc can be higher than 200 khz to achieve a 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden 70 at90s/ls8535 1041h ? 11/01 higher sampling rate. see ? adc characteristics ? on page 75 for more details. the adc module contains a prescaler, which divides the system clock to an acceptable adc clock frequency. the adps2..0 bits in adcsr are used to generate a proper adc clock input frequency from any cpu frequency above 100 khz. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsr. the prescaler keeps running for as long as the aden bit is set and is continuously reset when aden is low. when initiating a conversion by setting the adsc bit in adcsr, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles. in certain situations, the adc needs more clock cycles for initialization and to minimize offset errors. extended conversions take 25 adc clock cycles and occur as the first conversion after the adc is switched on (aden in adcsr is set). the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles after the start of an extended conversion. when a conversion is complete, the result is written to the adc data registers and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again and a new conversion will be initiated on the first rising adc clock edge. in free running mode, a new conversion will be started immediately after the conversion completes, while adsc remains high. using free running mode and an adc clock frequency of 200 khz gives the lowest conversion time with a maximum res- olution, 65 ?, equivalent to 15 ksps. for a summary of conversion times, see table 26. figure 47. adc timing diagram, extended conversion (single conversion mode) sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 extended conversion next conversion 3 mux and refs update mux and refs update conversion complete 71 at90s/ls8535 1041h ? 11/01 figure 48. adc timing diagram, single conversion figure 49. adc timing diagram, free running conversion adc noise canceler function the adc features a noise canceler that enables conversion during idle mode to reduce noise induced from the cpu core. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converting. single conver- sion mode must be selected and the adc conversion complete interrupt must be enabled. aden = 1 adsc = 0 adfr = 0 adie = 1 table 26. adc conversion time condition sample and hold (cycles from start of conversion) conversion time (cycles) conversion time (s) extended conversion 14 25 125 - 500 normal conversion 14 26 130 - 520 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 72 at90s/ls8535 1041h ? 11/01 2. enter idle mode. the adc will start a conversion once the cpu has been halted. 3. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the mcu and execute the adc conversion complete interrupt routine. adc multiplexer select register ? admux bits 7..3 ? res: reserved bits these bits are reserved bits in the at90s8535 and always read as zero. bits 2..0 ? mux2..mux0: analog channel select bits 2-0 the value of these three bits selects which analog input adc7..0 is connected to the adc. see table 27 for details. if these bits are changed during a conversion, the change will not go into effect until this conversion is complete (adif in adcsr is set). adc control and status register ? adcsr bit 7 ? aden: adc enable writing a logical ? 1 ? to this bit enables the adc. by clearing this bit to zero, the adc is turned off. turning the adc off while a conversion is in progress will terminate this conversion. bit 6 ? adsc: adc start conversion in single conversion mode, a logical ? 1 ? must be written to this bit to start each conver- sion. in free running mode, a logical ? 1 ? must be written to this bit to start the first conversion. the first time adsc has been written after the adc has been enabled or if adsc is written at the same time as the adc is enabled, an extended conversion will precede the initiated conversion. this extended conversion performs initialization of the adc. bit 76543210 $07 ($27) ????? mux2 mux1 mux0 admux read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 27. input channel selections mux2.0 single-ended input 000 adc0 001 adc1 010 adc2 011 adc3 100 adc4 101 adc5 110 adc6 111 adc7 bit 76543210 $06 ($26) aden adsc adfr adif adie adps2 adps1 adps0 adcsr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 73 at90s/ls8535 1041h ? 11/01 adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. when a extended conversion precedes a real conversion, adsc will stay high until the real conversion completes. writing a ? 0 ? to this bit has no effect. bit 5 ? adfr: adc free running select when this bit is set (one), the adc operates in free running mode. in this mode, the adc samples and updates the data registers continuously. clearing this bit (zero) will terminate free running mode. bit 4 ? adif: adc interrupt flag this bit is set (one) when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i- bit in sreg are set (one). adif is cleared by hardware when executing the correspond- ing interrupt handling vector. alternatively, adif is cleared by writing a logical ? 1 ? to the flag. beware that if doing a read-modify-write on adcsr, a pending interrupt can be dis- abled. this also applies if the sbi and cbi instructions are used. bit 3 ? adie: adc interrupt enable when this bit is set (one) and the i-bit in sreg is set (one), the adc conversion com- plete interrupt is activated. bits 2..0 ? adps2..adps0: adc prescaler select bits these bits determine the division factor between the xtal frequency and the input clock to the adc. adc data register ? adcl and adch when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated until adch is read. conse- quently, it is essential that both registers are read and that adcl is read before adch. table 28. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 151413121110 9 8 $05 ($25) ?????? adc9 adc8 adch $04 ($24) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 74 at90s/ls8535 1041h ? 11/01 adc9..0: adc conversion result these bits represent the result from the conversion. $000 represents analog ground and $3ff represents the selected reference voltage minus one lsb. scanning multiple channels since change of analog channel always is delayed until a conversion is finished, the free running mode can be used to scan multiple channels without interrupting the con- verter. typically, the adc conversion complete interrupt will be used to perform the channel shift. however, the user should take the following fact into consideration: the interrupt triggers once the result is ready to be read. in free running mode, the next conversion will start immediately when the interrupt triggers. if admux is changed after the interrupt triggers, the next conversion has already started and the old setting is used. adc noise canceling techniques digital circuitry inside and outside the at90s8535 generates emi that might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. the analog part of the at90s8535 and all analog components in the application should have a separate analog ground plane on the pcb. this ground plane is connected to the digital ground plane via a single point on the pcb. 2. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane and keep them well away from high-speed switching digital tracks. 3. the av cc pin on the at90s8535 should be connected to the digital v cc supply voltage via an lc network as shown in figure 50. 4. use the adc noise canceler function to reduce induced noise from the cpu. 5. if some port a pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 50. adc power connections gnd vcc pa0 (adc0) pa1 (adc1) pa2 (adc2) pa3 (adc3) pa4 (adc4) pa5 (adc5) pa6 (adc6) pa7 (adc7) aref avcc agnd pc0 100nf analog ground plane at90s8535 39 35 37 33 32 38 34 36 43 41 42 40 44 1 10 ? 75 at90s/ls8535 1041h ? 11/01 notes: 1. minimum for av cc is 2.7v. 2. maximum for av cc is 6.0v. adc characteristics t a = -40 c to 85 c symbol parameter condition min typ max units resolution 10 bits absolute accuracy vref = 4v adc clock = 200 khz 12lsb absolute accuracy vref = 4v adc clock = 1 mhz 4lsb absolute accuracy vref = 4v adc clock = 2 mhz 16 lsb integral non-linearity v ref > 2v 0.5 lsb differential non-linearity v ref > 2v 0.5 lsb zero error (offset) 1 lsb conversion time 65 260 s clock frequency 50 200 khz av cc analog supply voltage v cc - 0.3 (1) v cc + 0.3 (2) v v ref reference voltage 2 av cc v r ref reference input resistance 6 10 13 k ? v in input voltage agnd aref v r ain analog input resistance 100 m ? 76 at90s/ls8535 1041h ? 11/01 i/o ports all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the sbi and cbi instructions. the same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). port a port a is an 8-bit bi-directional i/o port. three i/o memory address locations are allocated for port a, one each for the data register ? porta, $1b($3b), data direction register ? ddra, $1a($3a) and the port a input pins ? pina, $19($39). the port a input pins address is read-only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port a output buffers can sink 20 ma and thus drive led displays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. port a has an alternate function as analog inputs for the adc. if some port a pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. this might corrupt the result of the conversion. during power-down mode, the schmitt trigger of the digital input is disconnected. this allows analog signals that are close to v cc /2 to be present during power-down without causing excessive power consumption. port a data register ? porta port a data direction register ? ddra port a input pins address ? pina the port a input pins address (pina) is not a register; this address enables access to the physical value on each port a pin. when reading porta, the port a data latch is read and when reading pina, the logical values present on the pins are read. bit 76543210 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $19 ($39) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 77 at90s/ls8535 1041h ? 11/01 port a as general digital i/o all eight pins in port a have equal functionality when used as digital i/o pins. pan, general i/o pin: the ddan bit in the ddra register selects the direction of this pin. if ddan is set (one), pan is configured as an output pin. if ddan is cleared (zero), pan is configured as an input pin. if portan is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portan has to be cleared (zero) or the pin has to be configured as an output pin.the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. note: n: 7,6 ? 0, pin number. port a schematics note that all port pins are synchronized. the synchronization latch is, however, not shown in the figure. figure 51. port a schematic diagrams (pins pa0 - pa7) table 29. ddan effects on port a pins ddan portan i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pan will source current if ext. pulled low 1 0 output no push-pull zero output 1 1 output no push-pull one output da ta bus d d q q reset reset c c wd wp rd mos pull- up pan adcn to adc mux wp: wd: rl: rp: rd: n: write porta write ddra read porta latch read porta pin read ddra 0-7 ddan portan rl rp pwrdn 78 at90s/ls8535 1041h ? 11/01 port b port b is an 8-bit bi-directional i/o port. three i/o memory address locations are allocated for the port b, one each for the data register ? portb, $18($38), data direction register ? ddrb, $17($37) and the port b input pins ? pinb, $16($36). the port b input pins address is read-only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port b output buffers can sink 20 ma and thus drive led displays directly. when pins pb0 to pb7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. the port b pins with alternate functions are shown in table 30. when the pins are used for the alternate function, the ddrb and portb registers have to be set according to the alternate function description. port b data register ? portb port b data direction register ? ddrb port b input pins address ? pinb the port b input pins address (pinb) is not a register and this address enables access to the physical value on each port b pin. when reading portb, the port b data latch is read and when reading pinb, the logical values present on the pins are read. table 30. port b pin alternate functions port pin alternate functions pb0 t0 (timer/counter0 external counter input) pb1 t1 (timer/counter1 external counter input) pb2 ain0 (analog comparator positive input) pb3 ain1 (analog comparator negative input) pb4 ss (spi slave select input) pb5 mosi (spi bus master output/slave input) pb6 miso (spi bus master input/slave output) pb7 sck (spi bus serial clock) bit 76543210 $18 ($38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $17 ($37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $16 ($36) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 79 at90s/ls8535 1041h ? 11/01 port b as general digital i/o all eight pins in port b have equal functionality when used as digital i/o pins. pbn, general i/o pin: the ddbn bit in the ddrb register selects the direction of this pin. if ddbn is set (one), pbn is configured as an output pin. if ddbn is cleared (zero), pbn is configured as an input pin. if portbn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portbn has to be cleared (zero) or the pin has to be configured as an output pin. the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. note: n: 7,6 ? 0, pin number. alternate functions of port b the alternate pin configuration is as follows: sck ? port b, bit 7 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb7. when the spi is enabled as a master, the data direction of this pin is controlled by ddb7. when the pin is forced to be an input, the pull-up can still be controlled by the portb7 bit. see the description of the spi port for further details. miso ? port b, bit 6 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb6. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb6. when the pin is forced to be an input, the pull-up can still be controlled by the portb6 bit. see the description of the spi port for further details. mosi ? port b, bit 5 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forced to be an input, the pull-up can still be controlled by the portb5 bit. see the description of the spi port for further details. ss ? port b, bit 4 ss : slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb4. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is con- trolled by ddb4. when the pin is forced to be an input, the pull-up can still be controlled by the portb4 bit. see the description of the spi port for further details. ain1 ? port b, bit 3 ain1, analog comparator negative input. when configured as an input (ddb3 is cleared [zero]) and with the internal mos pull-up resistor switched off (pb3 is cleared [zero]), this pin also serves as the negative input of the on-chip analog comparator. during power-down mode, the schmitt trigger of the digital input is disconnected. this table 31. ddbn effects on port b pins ddbn portbn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pbn will source current if ext. pulled low 1 0 output no push-pull zero output 1 1 output no push-pull one output 80 at90s/ls8535 1041h ? 11/01 allows analog signals that are close to v cc /2 to be present during power-down without causing excessive power consumption. ain0 ? port b, bit 2 ain0, analog comparator positive input. when configured as an input (ddb2 is cleared [zero]) and with the internal mos pull-up resistor switched off (pb2 is cleared [zero]), this pin also serves as the positive input of the on-chip analog comparator. during power-down mode, the schmitt trigger of the digital input is disconnected. this allows analog signals that are close to v cc /2 to be present during power-down without causing excessive power consumption. t1 ? port b, bit 1 t1, timer/counter1 counter source. see the timer description for further details. t0 ? port b, bit 0 t0: timer/counter0 counter source. see the timer description for further details. port b schematics note that all port pins are synchronized. the synchronization latches are, however, not shown in the figures. figure 52. port b schematic diagram (pins pb0 and pb1) 2 81 at90s/ls8535 1041h ? 11/01 figure 53. port b schematic diagram (pins pb2 and pb3) figure 54. port b schematic diagram (pin pb4) da ta bus d d q q reset reset c c wd wp rd mos pull- up pbn ainm to comparator wp: wd: rl: rp: rd: n: m: write portb write ddrb read portb latch read portb pin read ddrb 2, 3 0, 1 pwrdn ddbn portbn rl rp data bus d d q q reset reset c c wd wp rd mos pull- up pb4 spi ss mstr spe wp: wd: rl: rp: rd: mstr: spe: write portb write ddrb read portb latch read portb pin read ddrb spi master enable spi enable ddb4 portb4 rl rp 82 at90s/ls8535 1041h ? 11/01 figure 55. port b schematic diagram (pin pb5) figure 56. port b schematic diagram (pin pb6) data bus d d q q reset reset c c wd wp rd mos pull- up pb5 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb5 portb5 spe mstr spi master out spi slave in rl rp da ta bus d d q q reset reset c c wd wp rd mos pull- up pb6 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb6 portb6 spe mstr spi slave out spi master in rl rp 83 at90s/ls8535 1041h ? 11/01 figure 57. port b schematic diagram (pin pb7) da ta bus d d q q reset reset c c wd wp rd mos pull- up pb7 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb7 portb7 spe mstr spi clock out spi clock in rl rp 84 at90s/ls8535 1041h ? 11/01 port c port c is an 8-bit bi-directional i/o port. three i/o memory address locations are allocated for the port c, one each for the data register ? portc, $15($35), data direction register ? ddrc, $14($34) and the port c input pins ? pinc, $13($33). the port c input pins address is read-only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port c output buffers can sink 20 ma and thus drive led displays directly. when pins pc0 to pc7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. port c data register ? portc port c data direction register ? ddrc port c input pins address ? pinc the port c input pins address (pinc) is not a register; this address enables access to the physical value on each port c pin. when reading portc, the port c data latch is read and when reading pinc, the logical values present on the pins are read. port c as general digital i/o all eight pins in port c have equal functionality when used as digital i/o pins. pcn, general i/o pin: the ddcn bit in the ddrc register selects the direction of this pin. if ddcn is set (one), pcn is configured as an output pin. if ddcn is cleared (zero), pcn is configured as an input pin. if portcn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, portcn has to be cleared (zero) or the pin has to be configured as an output pin.the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. note: n: 7 ? 0, pin number bit 76543210 $15 ($35) portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $14 ($34) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $13 ($33) pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a table 32. ddcn effects on port c pins ddcn portcn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pcn will source current if ext. pulled low 1 0 output no push-pull zero output 1 1 output no push-pull one output 85 at90s/ls8535 1041h ? 11/01 alternate functions of port c when the as2 bit in assr is set (one) to enable asynchronous clocking of timer/counter2, pins pc6 and pc7 are disconnected from the port. in this mode, a crystal oscillator is connected to the pins and the pins cannot be used as i/o pins. port c schematics note that all port pins are synchronized. the synchronization latch is, however, not shown in the figure. figure 58. port c schematic diagram (pins pc0 - pc5) figure 59. port c schematic diagram (pins pc6) da ta bus d d q q reset reset c c wd wp rd mos pull- up pcn r r wp: wd: rl: rp: rd: n: write portc write ddrc read portc latch read portc pin read ddrc 0-5 ddcn portcn rl rp da ta bus d d q q reset reset c c wd wp rd mos pull- up pc6 r r wp: wd: rl: rp: rd: as2: write portc write ddrc read portc latch read portc pin read ddrc asynch select t/c2 ddc6 portc6 rl rp as2 t/c2 osc amp inpu t 86 at90s/ls8535 1041h ? 11/01 figure 60. port c schematic diagram (pins pc7) port d port d is an 8-bit bi-directional i/o port with internal pull-up resistors. three i/o memory address locations are allocated for port d, one each for the data register ? portd, $12($32), data direction register ? ddrd, $11($31) and the port d input pins ? pind, $10($30). the port d input pins address is read-only, while the data register and the data direction register are read/write. the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. some port d pins have alternate functions as shown in table 33. table 33. port d pin alternate functions port pin alternate function pd0 rxd (uart input line) pd1 txd (uart output line) pd2 int0 (external interrupt 0 input) pd3 int1 (external interrupt 1 input) pd4 oc1b (timer/counter1 output compareb match output) pd5 oc1a (timer/counter1 output comparea match output) pd6 icp (timer/counter1 input capture pin) pd7 oc2 (timer/counter2 output compare match output) 87 at90s/ls8535 1041h ? 11/01 port d data register ? portd port d data direction register ? ddrd port d input pins address ? pind the port d input pins address (pind) is not a register; this address enables access to the physical value on each port d pin. when reading portd, the port d data latch is read and when reading pind, the logical values present on the pins are read. port d as general digital i/o pdn, general i/o pin: the dddn bit in the ddrd register selects the direction of this pin. if dddn is set (one), pdn is configured as an output pin. if dddn is cleared (zero), pdn is configured as an input pin. if pdn is set (one) when configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the pdn has to be cleared (zero) or the pin has to be configured as an output pin.the port pins are tri- stated when a reset condition becomes active, even if the clock is not running. note: n: 7,6 ? 0, pin number. alternate functions of port d oc2 ? port d, bit 7 oc2, timer/counter2 output compare match output: the pd7 pin can serve as an external output for the timer/counter2 output compare. the pin has to be configured as an output (ddd7 set [one]) to serve this function. see the timer description on how to enable this function. the oc2 pin is also the output pin for the pwm mode timer function. icp ? port d, bit 6 icp ? input capture pin: the pd6 pin can act as an input capture pin for timer/counter1. the pin has to be configured as an input (ddd6 cleared [zero]) to serve this function. see the timer description on how to enable this function. bit 76543210 $12 ($32) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $11 ($31) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $10 ($30) pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a table 34. dddn bits on port d pins dddn portdn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pdn will source current if ext. pulled low 1 0 output no push-pull zero output 1 1 output no push-pull one output 88 at90s/ls8535 1041h ? 11/01 oc1a ? port d, bit 5 oc1a, output compare matcha output: the pd5 pin can serve as an external output for the timer/counter1 output comparea. the pin has to be configured as an output (ddd5 set [one]) to serve this function. see the timer description on how to enable this function. the oc1a pin is also the output pin for the pwm mode timer function. oc1b ? port d, bit 4 oc1b, output compare matchb output: the pd4 pin can serve as an external output for the timer/counter1 output compareb. the pin has to be configured as an output (ddd4 set [one]) to serve this function. see the timer description on how to enable this function. the oc1b pin is also the output pin for the pwm mode timer function. int1 ? port d, bit 3 int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source to the mcu. see the interrupt description for further details and how to enable the source. int0 ? port d, bit 2 int0, external interrupt source 0: the pd2 pin can serve as an external interrupt source to the mcu. see the interrupt description for further details and how to enable the source. txd ? port d, bit 1 transmit data (data output pin for the uart). when the uart transmitter is enabled, this pin is configured as an output, regardless of the value of ddd1. rxd ? port d, bit 0 receive data (data input pin for the uart). when the uart receiver is enabled, this pin is configured as an input, regardless of the value of ddd0. when the uart forces this pin to be an input, a logical ? 1 ? in portd0 will turn on the internal pull-up. 89 at90s/ls8535 1041h ? 11/01 port d schematics note that all port pins are synchronized. the synchronization latches are, however, not shown in the figures. figure 61. port d schematic diagram (pin pd0) figure 62. port d schematic diagram (pin pd1) da ta bus d d q q reset reset c c wd wp rd mos pull- up pd0 rxd rxen wp: wd: rl: rp: rd: rxd: rxen: write portd write ddrd read portd latch read portd pin read ddrd uart receive data uart receive enable ddd0 portd0 rl rp da ta bus d d q q reset reset c c wd wp rd rp rl mos pull- up pd1 r r wp: wd: rl: rp: rd: txd: txen: write portd write ddrd read portd latch read portd pin read ddrd uart transmit data uart transmit enable ddd1 portd1 txen txd 90 at90s/ls8535 1041h ? 11/01 figure 63. port d schematic diagram (pins pd2 and pd3) figure 64. port d schematic diagram (pins pd4 and pd5) 91 at90s/ls8535 1041h ? 11/01 figure 65. port d schematic diagram (pin pd6) figure 66. port d schematic diagram (pin pd7) data bus d d q q reset reset c c wd wp rd mos pull- up pd6 r r wp: wd: rl: rp: rd: acic: aco: write portd write ddrd read portd latch read portd pin read ddrd comparator ic enable comparator output ddd6 portd6 noise canceler edge select icf1 icnc1 ices1 0 1 acic aco rl rp 92 at90s/ls8535 1041h ? 11/01 memory programming program and data memory lock bits the at90s8535 mcu provides two lock bits that can be left unprogrammed ( ? 1 ? ) or can be programmed ( ? 0 ? ) to obtain the additional features listed in table 35. the lock bits can only be erased with the chip erase command. note: 1. in parallel mode, further programming of the fuse bits is also disabled. program the fuse bits before programming the lock bits. fuse bits the at90s8535 has two fuse bits, spien and fstrt. when the spien fuse is programmed ( ? 0 ? ), serial program and data downloading is enabled. default value is programmed ( ? 0 ? ). the spien fuse is not accessible in serial programming mode. when the fstrt fuse is programmed ( ? 0 ? ), the short start-up time is selected. default value is unprogrammed ( ? 1 ? ). the status of the fuse bits is not affected by chip erase. signature bytes all atmel microcontrollers have a three-byte signature code that identifies the device. this code can be read in both serial and parallel modes. the three bytes reside in a separate address space. 1. $000: $1e (indicates manufactured by atmel) 2. $001: $93 (indicates 8k bytes flash memory) 3. $002: $03 (indicates at90s8535 device when signature byte $001 is $93) note: 1. when both lock bits are programmed (lock mode 3), the signature bytes cannot be read in serial mode. reading the signature bytes will return: $00, $01 and $02. programming the flash and eeprom atmel ? s at90s8535 offers 8k bytes of in-system reprogrammable flash program mem- ory and 512 bytes of eeprom data memory. the at90s8535 is shipped with the on-chip flash program and eeprom data memory arrays in the erased state (i.e., contents = $ff) and ready to be programmed. this device supports a high-voltage (12v) parallel programming mode and a low-voltage serial programming mode. the +12v is used for programming enable only and no cur- rent of significance is drawn by this pin. the serial programming mode provides a convenient way to download program and data into the at90s8535 inside the user ? s system. the program and data memory arrays on the at90s8535 are programmed byte-by-byte in either programming mode. for the eeprom, an auto-erase cycle is provided within the self-timed write instruction in the serial programming mode. during programming, the supply voltage must be in accordance with table 36. table 35. lock bit protection modes memory lock bits protection type mode lb1 lb2 1 1 1 no memory lock features enabled. 2 0 1 further programming of the flash and eeprom is disabled. (1) 3 0 0 same as mode 2 and verify is also disabled. 93 at90s/ls8535 1041h ? 11/01 parallel programming this section describes how to parallel program and verify flash program memory, eeprom data memory, lock bits and fuse bits in the at90s8535. signal names in this section, some pins of the at90s8535 are referenced by signal names describing their function during parallel programming. see figure 67 and table 37. pins not described in table 37 are referenced by pin name. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a posi- tive pulse. the bit coding are shown in table 38. when pulsing wr or oe , the command loaded determines the action executed. the command is a byte where the different bits are assigned functions as shown in table 39. figure 67. parallel programming table 36. supply voltage during programming part serial programming parallel programming at90s8535 4.0 - 6.0v 4.5 - 5.5v at90ls8535 2.7 - 6.0v 4.5 - 5.5v at90s8535 vcc +5v reset gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 +12 v rdy/bsy oe bs xa0 xa1 wr pb7 - pb0 data 94 at90s/ls8535 1041h ? 11/01 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply supply voltage according to table 36, between v cc and gnd. 2. set the reset and bs pin to ? 0 ? and wait at least 100 ns. 3. apply 11.5 - 12.5v to reset . any activity on bs within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. table 37. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs pd4 i byte select ( ? 0 ? selects low byte, ? 1 ? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 data pb7 - 0 i/o bi-directional data bus (output when oe is low) table 38. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs) 0 1 load data (high or low data byte for flash determined by bs) 1 0 load command 1 1 no action, idle table 39. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes 0000 0100 read lock and fuse bits 0000 0010 read flash 0000 0011 read eeprom 95 at90s/ls8535 1041h ? 11/01 chip erase the chip erase command will erase the flash and eeprom memories and the lock bits. the lock bits are not reset until the flash and eeprom have been completely erased. the fuse bits are not changed. chip erase must be performed before the flash or eeprom is reprogrammed. load command ? chip erase ? : 1. set xa1, xa0 to ? 10 ? . this enables command loading. 2. set bs to ? 0 ? . 3. set data to ? 1000 0000 ? . this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a t wlwh_ce -wide negative pulse to execute chip erase. see table 40 for t wlwh_ce value. chip erase does not generate any activity on the rdy/bsy pin. programming the flash a: load command ? write flash ? 1. set xa1, xa0 to ? 10 ? . this enables command loading. 2. set bs to ? 0 ? . 3. set data to ? 0001 0000 ? . this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b: load address high byte 1. set xa1, xa0 to ? 00 ? . this enables address loading. 2. set bs to ? 1 ? . this selects high byte. 3. set data = address high byte ($00 - $0f). 4. give xtal1 a positive pulse. this loads the address high byte. c: load address low byte 1. set xa1, xa0 to ? 00 ? . this enables address loading. 2. set bs to ? 0 ? . this selects low byte. 3. set data = address low byte ($00 - $ff). 4. give xtal1 a positive pulse. this loads the address low byte. d: load data low byte 1. set xa1, xa0 to ? 01 ? . this enables data loading. 2. set data = data low byte ($00 - $ff). 3. give xtal1 a positive pulse. this loads the data low byte. e: write data low byte 1. set bs to ? 0 ? . this selects low data. 2. give wr a negative pulse. this starts programming of the data byte. rdy/bsy goes low. 3. wait until rdy/bsy goes high to program the next byte. (see figure 68 for signal waveforms.) f: load data high byte 1. set xa1, xa0 to ? 01 ? . this enables data loading. 2. set data = data high byte ($00 - $ff). 3. give xtal1 a positive pulse. this loads the data high byte. g: write data high byte 96 at90s/ls8535 1041h ? 11/01 1. set bs to ? 1 ? . this selects high data. 2. give wr a negative pulse. this starts programming of the data byte. rdy/bsy goes low. 3. wait until rdy/bsy goes high to program the next byte. (see figure 69 for signal waveforms.) the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered: the command needs only be loaded once when writing or reading multiple memory locations. address high byte needs only be loaded before programming a new 256-word page in the flash. skip writing the data value $ff, that is, the contents of the entire flash and eeprom after a chip erase. these considerations also apply to eeprom programming and flash, eeprom and signature byte reading. figure 68. programming the flash waveforms $10 addr. high addr. low data low data xa1 xa0 bs xtal1 wr rdy/bsy reset oe 12v 97 at90s/ls8535 1041h ? 11/01 figure 69. programming the flash waveforms (continued) reading the flash the algorithm for reading the flash memory is as follows (refer to ? programming the flash ? for details on command and address loading): 1. a: load command ? 0000 0010 ? . 2. b: load address high byte ($00 - $0f). 3. c: load address low byte ($00 - $ff). 4. set oe to ? 0 ? and bs to ? 0 ? . the flash word low byte can now be read at data. 5. set bs to ? 1 ? . the flash word high byte can now be read from data. 6. set oe to ? 1 ? . programming the eeprom the programming algorithm for the eeprom data memory is as follows (refer to ? pro- gramming the flash ? for details on command, address and data loading): 1. a: load command ? 0001 0001 ? . 2. b: load address high byte ($00 - $01). 3. c: load address low byte ($00 - $ff). 4. d: load data low byte ($00 - $ff). 5. e: write data low byte. reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ? programming the flash ? for details on command and address loading): 1. a: load command ? 0000 0011 ? . 2. b: load address high byte ($00 - $01). 3. c: load address low byte ($00 - $ff). 4. set oe to ? 0 ? and bs to ? 0 ? . the eeprom data byte can now be read at data. 5. set oe to ? 1 ? . data high data xa1 xa0 bs xtal1 wr rdy/bsy reset +12v oe 98 at90s/ls8535 1041h ? 11/01 programming the fuse bits the algorithm for programming the fuse bits is as follows (refer to ? programming the flash ? for details on command and data loading): 1. a: load command ? 0100 0000 ? . 2. d: load data low byte. bit n = ? 0 ? programs and bit n = ? 1 ? erases the fuse bit. bit 5 = spien fuse bit. bit 0 = fstrt fuse bit. bit 7-6,4-1 = ? 1 ? . these bits are reserved and should be left unprogrammed ( ? 1 ? ). 3. give wr a t wlwh_pfb -wide negative pulse to execute the programming, t wlwh_pfb is found in table 40. programming the fuse bits does not generate any activity on the rdy/bsy pin. programming the lock bits the algorithm for programming the lock bits is as follows (refer to ? programming the flash ? on page 95 for details on command and data loading): 1. a: load command ? 0010 0000 ? . 2. d: load data low byte. bit n = ? 0 ? programs the lock bit. bit 2 = lock bit2 bit 1 = lock bit1 bit 7-3,0 = ? 1 ? . these bits are reserved and should be left unprogrammed ( ? 1 ? ). 3. e: write data low byte. the lock bits can only be cleared by executing chip erase. reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ? programming the flash ? on page 95 for details on command loading): 1. a: load command ? 0000 0100 ? . 2. set oe to ? 0 ? and bs to ? 1 ? . the status of the fuse and lock bits can now be read at data ( ? 0 ? means programmed). bit 7 = lock bit1 bit 6 = lock bit2 bit 5 = spien fuse bit bit 0 = fstrt fuse bit 3. set oe to ? 1 ? . observe that bs needs to be set to ? 1 ? . reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ? programming the flash ? on page 95 for details on command and address loading): 1. a: load command ? 0000 1000 ? . 2. c: load address low byte ($00 - $02). set oe to ? 0 ? and bs to ? 0 ? . the selected signature byte can now be read at data. 3. set oe to ? 1 ? . 99 at90s/ls8535 1041h ? 11/01 parallel programming characteristics figure 70. parallel programming timing notes: 1. use t wlwh_ce for chip erase and t wlwh_pfb for programming the fuse bits. 2. if t wlwh is held longer than t wlrh , no rdy/bsy pulse will be seen. serial downloading both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output), see figure 71. after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. table 40. parallel programming characteristics, t a = 25 c 10%, v cc = 5v ?10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250.0 a t dvxh data and control setup before xtal1 high 67.0 ns t xhxl xtal1 pulse width high 67.0 ns t xldx data and control hold after xtal1 low 67.0 ns t xlwl xtal1 low to wr low 67.0 ns t bvwl bs valid to wr low 67.0 ns t rhbx bs hold after rdy/bsy high 67.0 ns t wlwh wr pulse width low (1) 67.0 ns t whrl wr high to rdy/bsy low (2) 20.0 ns t wlrh wr low to rdy/bsy high (2) 0.5 0.7 0.9 ms t xlol xtal1 low to oe low 67.0 ns t oldv oe low to data valid 20.0 ns t ohdz oe high to data tri-stated 20.0 ns t wlwh_ce wr pulse width low for chip erase 5.0 10.0 15.0 ms t wlwh_pfb wr pulse width low for programming the fuse bits 1.0 1.5 1.8 ms data & contol (data, xa0/1, bs) data write read xtal1 t xhxl t wlwh t dvxh t xlol t oldv t whrl t wlrh wr rdy/bsy oe t xldx t xlwl t rhbx t ohdz t bvwl 100 at90s/ls8535 1041h ? 11/01 figure 71. serial programming and verify for the eeprom, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the chip erase instruction. the chip erase instruc- tion turns the content of every memory location in both the program and eeprom arrays into $ff. the program and eeprom memory arrays have separate address spaces: $0000 to $0fff for program memory and $0000 to $01ff for eeprom memory. either an external clock is supplied at pin xtal1 or a crystal needs to be connected across pins xtal1 and xtal2. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 xtal1 clock cycles high: > 2 xtal1 clock cycles serial programming algorithm when writing serial data to the at90s8535, data is clocked on the rising edge of sck. when reading data from the at90s8535, data is clocked on the falling edge of sck. see figure 72, figure 73 and table 43 for timing details. to program and verify the at90ss8535 in the serial programming mode, the following sequence is recommended (see 4-byte instruction formats in table 42 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ? 0 ? . if a crys- tal is not connected across pins xtal1 and xtal2, apply a clock signal to the xtal1 pin. in some systems, the programmer cannot guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two xtal1 cycles duration after sck has been set to ? 0 ? . 2. wait for at least 20 ms and enable serial programming by sending the program- ming enable serial instruction to the mosi (pb5) pin. 3. the serial programming instructions will not work if the communication is out of synchronization. when in sync, the second byte ($53) will echo back when issu- ing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the $53 did not echo back, give sck a positive pulse and issue a new programming enable instruction. if the $53 is not seen within 32 attempts, there is no functional device connected. at90s8535 vcc 2.7 - 6.0v pb7 pb6 pb5 reset gnd xtal1 sck miso mosi gnd clock input 101 at90s/ls8535 1041h ? 11/01 4. if a chip erase is performed (must be done to erase the flash), wait t wd_erase after the instruction, give reset a positive pulse and start over from step 2. see table 44 for t wd_erase value. 5. the flash or eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. use data polling to detect when the next byte in the flash or eeprom can be writ- ten. if polling is not used, wait t wd_prog before transmitting the next instruction. see table 45 for t wd_prog value. in an erased device, no $ffs in the data file(s) needs to be programmed. 6. any memory location can be verified by using the read instruction that returns the content at the selected address at the serial output miso (pb6) pin. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set xtal1 to ? 0 ? (if a crystal is not used). set reset to ? 1 ? . turn v cc power off. data polling eeprom when a byte is being programmed into the eeprom, reading the address location being programmed will give the value p1 until the auto-erase is finished and then the value p2. see table 41 for p1 and p2 values. at the time the device is ready for a new eeprom byte, the programmed value will read correctly. this is used to determine when the next byte can be written. this will not work for the values p1 and p2, so when programming these values, the user will have to wait for at least the prescribed time t wd_prog before programming the next byte. see table 45 for t wd_prog value. as a chip-erased device contains $ff in all locations, program- ming of addresses that are meant to contain $ff can be skipped. this does not apply if the eeprom is reprogrammed without first chip-erasing the device. data polling flash when a byte is being programmed into the flash, reading the address location being programmed will give the value $ff. at the time the device is ready for a new byte, the programmed value will read correctly. this is used to determine when the next byte can be written. this will not work for the value $ff, so when programming this value, the user will have to wait for at least t wd_prog before programming the next byte. as a chip- erased device contains $ff in all locations, programming of addresses that are meant to contain $ff can be skipped. figure 72. serial programming waveforms table 41. read back value during eeprom polling part p1 p2 at90s/ls8535 $00 $ff msb msb lsb lsb serial clock input pb7(sck) serial data input pb5(mosi) serial data output pb6(miso) 102 at90s/ls8535 1041h ? 11/01 f notes: 1. a = address high bits b = address low bits h = 0 ? low byte, 1 ? high byte o = data out i = data in x = don ? t care 1 = lock bit 1 2 = lock bit 2 f = fstrt fuse s = spien fuse 2. the signature bytes are not readable in lock mode 3, i.e., both lock bits programmed. table 42. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming while reset is low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase flash and eeprom memory arrays. read program memory 0010 h 000 xxxx aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . write program memory 0100 h 000 xxxx aaaa bbbb bbbb iiii iiii write h (high or low) data i to program memory at word address a : b . read eeprom memory 1010 0000 xxxx xxx a bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 xxxx xxx a bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . read lock and fuse bits 0101 1000 xxxx xxxx xxxx xxxx 12 s x xxx f read lock and fuse bits. ? 0 ? = programmed ? 1 ? = unprogrammed write lock bits 1010 1100 1111 1 21 1 xxxx xxxx xxxx xxxx write lock bits. set bits 1 , 2 = ? 0 ? to program lock bits. read signature byte 0011 0000 xxxx xxxx xxxx xx bb oooo oooo read signature byte o at address b . (2) write fstrt fuse 1010 1100 1011 111 f xxxx xxxx xxxx xxxx write fstrt fuse. set bit f = ? 0 ? to program, ? 1 ? to unprogram. 103 at90s/ls8535 1041h ? 11/01 serial programming characteristics figure 73. serial programming timing table 43. serial programming characteristics, t a = -40 c to 85 c, v cc = 2.7 - 6.0v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency (v cc = 2.7 - 6.0v) 0 4.0 mhz t clcl oscillator period (v cc = 2.7 - 4.0v) 250.0 ns 1/t clcl oscillator frequency (v cc = 4.0 - 6.0v) 0 8.0 mhz t clcl oscillator period (v cc = 4.0 - 6.0v) 125.0 ns t shsl sck pulse width high 2.0 t clcl ns t slsh sck pulse width low 2.0 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2.0 t clcl ns t sliv sck low to miso valid 10.0 16.0 32.0 ns table 44. minimum wait delay after the chip erase instruction symbol 3.2v 3.6v 4.0v 5.0v t wd_erase 18 ms 14 ms 12 ms 8 ms table 45. minimum wait delay after writing a flash or eeprom location symbol 3.2v 3.6v 4.0v 5.0v t wd_prog 9 ms 7 ms 6 ms 4 ms mosi miso sck t ovsh t shsl t slsh t shox t sliv 104 at90s/ls8535 1041h ? 11/01 electrical characteristics absolute maximum ratings* operating temperature ................................ -40 c to +105 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c voltage on any pin except reset with respect to ground .............................-1.0v to v cc + 0.5v voltage on reset with respect to ground ....-1.0v to +13.0v maximum operating voltage ............................................ 6.6v i/o pin maximum current ........................................... 40.0 ma maximum current v cc and gnd (pdip package) ....................................... 200.0 ma maximum current v cc and gnd (tqfp, plcc package) ............................ 400.0 ma dc characteristics t a = -40 c to 85 c, v cc = 2.7v to 6.0v (unless otherwise noted) symbol parameter condition min typ max units v il input low voltage -0.5 0.3v cc (1) v v il1 input low voltage xtal -0.5 0.2 v cc (1) v v ih input high voltage except (xtal, reset) 0.6 v cc (2) v cc + 0.5 v v ih1 input high voltage xtal 0.8 v cc (2) v cc + 0.5 v v ih2 input high voltage reset 0.9 v cc (2) v cc + 0.5 v v ol output low voltage (3) (ports a, b, c, d) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.6 0.5 v v v oh output high voltage (4) (ports a, b, c, d) i oh = -3 ma, v cc = 5v i oh = -1.5 ma, v cc = 3v 4.2 2.3 v v i il input leakage current i/o pin v cc = 6v, vin = 0.45v (absolute value) 8.0 a i ih input leakage current i/o pin v cc = 6v, vin = 6.0v (absolute value) 8.0 a rrst reset pull-up 100.0 500.0 k ? r i/o i/o pin pull-up resistor 35.0 120.0 k ? i cc power supply current active 4 mhz, v cc = 3v 5.0 ma idle 4 mhz, v cc = 3v 3.0 ma power-down, v cc = 3v wdt enabled (5) 15.0 ? power-down, v cc = 3v wdt disabled (5) 5.0 a power save, v cc = 3v wdt disabled (5) 15.0 ? 105 at90s/ls8535 1041h ? 11/01 notes: 1. ? max ? means the highest value where the pin is guaranteed to be read as low (logical ? 0 ? ). 2. ? min ? means the lowest value where the pin is guaranteed to be read as high (logical ? 1 ? ). 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: pdip package: 1] the sum of all i ol , for all ports, should not exceed 200 ma. 2] the sum of all i ol , for port a0 - a7, should not exceed 100 ma. 3] the sum of all i ol , for ports b0 - b7, c0 - c7, d0 - d7 and xtal2, should not exceed 100 ma. plcc and tqfp packages: 1] the sum of all i ol , for all ports, should not exceed 400 ma. 2] the sum of all i ol , for ports a0 - a7, should not exceed 100 ma. 3] the sum of all i ol , for ports b0 - b3, should not exceed 100 ma. 4] the sum of all i ol , for ports b4 - b7, should not exceed 100 ma. 5] the sum of all i ol , for ports c0 - c3, should not exceed 100 ma. 6] the sum of all i ol , for ports c4 - c7, should not exceed 100 ma. 7] the sum of all i ol , for ports d0 - d3 and xtal2, should not exceed 100 ma. 8] the sum of all i ol , for ports d4 - d7, should not exceed 100 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (3 ma at v cc = 5v, 1.5 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: pdip package: 1] the sum of all i oh , for all ports, should not exceed 200 ma. 2] the sum of all i oh , for port a0 - a7, should not exceed 100 ma. 3] the sum of all i oh , for ports b0 - b7, c0 - c7, d0 - d7 and xtal2, should not exceed 100 ma. plcc and tqfp packages: 1] the sum of all i oh , for all ports, should not exceed 400 ma. 2] the sum of all i oh , for ports a0 - a7, should not exceed 100 ma. 3] the sum of all i oh , for ports b0 - b3, should not exceed 100 ma. 4] the sum of all i oh , for ports b4 - b7, should not exceed 100 ma. 5] the sum of all i oh , for ports c0 - c3, should not exceed 100 ma. 6] the sum of all i oh , for ports c4 - c7, should not exceed 100 ma. 7] the sum of all i oh , for ports d0 - d3 and xtal2, should not exceed 100 ma. 8] the sum of all i oh , for ports d4 - d7, should not exceed 100 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 5. minimum v cc for power-down is 2v. v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 40.0 mv i aclk analog comparator input leakage a v cc = 5v v in = v cc /2 -50.0 50.0 na t acpd analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750.0 500.0 ns dc characteristics (continued) t a = -40 c to 85 c, v cc = 2.7v to 6.0v (unless otherwise noted) symbol parameter condition min typ max units 106 at90s/ls8535 1041h ? 11/01 external clock drive waveforms figure 74. external clock table 46. external clock drive symbol parameter v cc = 2.7v to 6.0v v cc = 4.0v to 6.0v units min max min max 1/t clcl oscillator frequency 0 4 0 8.0 mhz t clcl clock period 250.0 125.0 ns t chcx high time 100.0 50.0 ns t clcx low time 100.0 50.0 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s vil1 vih1 107 at90s/ls8535 1041h ? 11/01 typical characteristics the following charts show typical behavior. these figures are not tested during manu- facturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail- to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l v cc f where c l = load capacitance, v cc = operating voltage and f = average switch- ing frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. figure 75. active supply current vs. frequency active supply current vs. frequency t = 25?c a frequency (mhz) i cc (ma) v cc = 5.5v v cc = 5v 0 5 10 15 20 25 30 35 40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v cc = 2.7v v cc = 3.0v v cc = 3.3v v cc = 3.6v v cc = 4v v cc = 4.5v v cc = 6v 108 at90s/ls8535 1041h 11/01 figure 76. active supply current vs. v cc figure 77. idle supply current vs. frequency 0 2 4 6 8 10 12 14 16 2 2.5 3 3.5 4 4.5 5 5.5 6 active supply current vs. v cc frequency = 4 mhz i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v cc = 6v v cc = 5.5v v cc = 5v v cc = 4.5v v cc = 4v v cc = 3.6v v cc = 3.3v v cc = 3.0v v cc = 2.7v idle supply current vs. frequency t = 25 ? c a frequency (mhz) i cc (ma) 109 at90s/ls8535 1041h 11/01 figure 78. idle supply current vs. v cc figure 79. power-down supply current vs. v cc 0 1 2 3 4 5 6 7 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 25 ? c a t = 85 ? c a idle supply current vs. v cc i cc (ma) v cc (v) frequency = 4 mhz 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a power down supply current vs. v cc i cc (?) v cc (v) watchdog timer disabled t = 45 ? c a t = 70 ? c a 110 at90s/ls8535 1041h 11/01 figure 80. power-down supply current vs. v cc figure 81. power save supply current vs. v cc 0 20 40 60 80 100 120 140 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a power down supply current vs. v cc i cc (?) v cc (v) watchdog timer enabled 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a power save supply current vs. v cc i cc (?) v cc (v) watchdog timer disabled t = 25 ? c a 111 at90s/ls8535 1041h 11/01 figure 82. analog comparator current vs. v cc note: analog comparator offset voltage is measured as absolute offset. figure 83. analog comparator offset voltage vs. common mode voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 2.5 3 3.5 4 4.5 5 5.5 6 analog comparator current vs. v cc i cc (ma) v cc (v) t = 25 ? c a t = 85 ? c a 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 analog comparator offset voltage vs. v = 5v cc common mode voltage common mode voltage (v) offset voltage (mv) t = 85 ? c a t = 25 ? c a 112 at90s/ls8535 1041h 11/01 figure 84. analog comparator offset voltage vs. common mode voltage figure 85. analog comparator input leakage current 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 analog comparator offset voltage vs. common mode voltage common mode voltage (v) offset voltage (mv) v = 2.7v cc t = 85 ? c a t = 25 ? c a 60 50 40 30 20 10 0 -10 0 0.5 1.5 1 2 2.5 3.5 3 4 4.5 5 6 6.5 7 5.5 analog comparator input leakage current t = 25 ? c a i (na) aclk v (v) in v = 6v cc 113 at90s/ls8535 1041h 11/01 figure 86. watchdog oscillator frequency vs. v cc note: sink and source capabilities of i/o ports are measured on one pin at a time. figure 87. pull-up resistor current vs. input voltage 0 200 400 600 800 1000 1200 1400 1600 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a watchdog oscillator frequency vs. v cc v (v) cc f (khz) rc 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 pull-up resistor current vs. input voltage v = 5v cc i ( a) op v (v) op t = 85 ? c a t = 25 ? c a 114 at90s/ls8535 1041h 11/01 figure 88. pull-up resistor current vs. input voltage figure 89. i/o pin sink current vs. output voltage 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 pull-up resistor current vs. input voltage i ( a) op v (v) op v = 2.7v cc t = 85 ? c a t = 25 ? c a 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v = 5v cc i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a i/o pin sink current vs. output voltage 115 at90s/ls8535 1041h 11/01 figure 90. i/o pin source current vs. output voltage figure 91. i/o pin sink current vs. output voltage 0 2 4 6 8 10 12 14 16 18 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i/o pin source current vs. output voltage v = 5v cc i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 i/o pin source current vs. output voltage i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a v = 2.7v cc 116 at90s/ls8535 1041h 11/01 figure 92. i/o pin source current vs. output voltage figure 93. i/o pin input threshold voltage vs. v cc 0 5 10 15 20 25 0 0.5 1 1.5 2 i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a i/o pin sink current vs. output voltage v = 2.7v cc 0 0.5 1 1.5 2 2.5 2.7 4.0 5.0 threshold voltage (v) v cc i/o pin input threshold voltage vs. v cc t = 25 ? c a 117 at90s/ls8535 1041h 11/01 figure 94. i/o pin input hysteresis vs. v cc 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 2.7 4.0 5.0 input hysteresis (v) v cc i/o pin input hysteresis vs. v cc t = 25 ? c a 118 at90s/ls8535 1041h 11/01 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c page 19 $3e ($5e) sph - - - - - - sp9 sp8 page 20 $3d ($5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 20 $3c ($5c) reserved $3b ($5b) gimsk int1 int0 - - - - - - page 25 $3a ($5a) gifr intf1 intf0 page 26 $39 ($59) timsk ocie2 toie2 ticie1 ocie1a ocie1b toie1 - toie0 page 26 $38 ($58) tifr ocf2 tov2 icf1 ocf1a ocf1b tov1 - tov0 page 27 $37 ($57) reserved $36 ($56) reserved $35 ($55) mcucr - se sm1 sm0 isc11 isc10 isc01 isc00 page 29 $34 ($54) mcusr - - - - - - extrf porf page 24 $33 ($53) tccr0 - - - - - cs02 cs01 cs00 page 34 $32 ($52) tcnt0 timer/counter0 (8 bits) page 34 $31 ($51) reserved $30 ($50) reserved $2f ($4f) tccr1a com1a1 com1a0 com1b1 com1b0 - - pwm11 pwm10 page 36 $2e ($4e) tccr1b icnc1 ices1 - - ctc1 cs12 cs11 cs10 page 37 $2d ($4d) tcnt1h timer/counter1 counter register high byte page 38 $2c ($4c) tcnt1l timer/counter1 counter register low byte page 38 $2b ($4b) ocr1ah timer/counter1 output compare register a high byte page 39 $2a ($4a) ocr1al timer/counter1 output compare register a low byte page 39 $29 ($49) ocr1bh timer/counter1 output compare register b high byte page 39 $28 ($48) ocr1bl timer/counter1 output compare register b low byte page 39 $27 ($47) icr1h timer/counter1 input capture register high byte page 40 $26 ($46) icr1l timer/counter1 input capture register low byte page 40 $25 ($45) tccr2 - pwm2 com21 com20 ctc2 cs22 cs21 cs20 page 43 $24 ($44) tcnt2 timer/counter2 (8 bits) page 44 $23 ($43) ocr2 timer/counter2 output compare register page 44 $22 ($42) assr - - - - as2 tcn2ub ocr2ub tcr2ub page 46 $21 ($41) wdtcr - - - wdtoe wde wdp2 wdp1 wdp0 page 49 $20 ($40) reserved $1f ($3f) eearh eear8 page 51 $1e ($3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 51 $1d ($3d) eedr eeprom data register page 51 $1c ($3c) eecr - - - - eerie eemwe eewe eere page 51 $1b ($3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 76 $1a ($3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 76 $19 ($39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 76 $18 ($38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 78 $17 ($37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 78 $16 ($36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 78 $15 ($35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 page 84 $14 ($34) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 84 $13 ($33) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 page 84 $12 ($32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 87 $11 ($31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 87 $10 ($30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 page 87 $0f ($2f) spdr spi data register page 58 $0e ($2e) spsr spif wcol - - - - - - page 58 $0d ($2d) spcr spie spe dord mstr cpol cpha spr1 spr0 page 57 $0c ($2c) udr uart i/o data register page 62 $0b ($2b) usr rxc txc udre fe or - - - page 62 $0a ($2a) ucr rxcie txcie udrie rxen txen chr9 rxb8 txb8 page 63 $09 ($29) ubrr uart baud rate register page 65 $08 ($28) acsr acd - aco aci acie acic acis1 acis0 page 66 $07 ($27) admux - - - - - mux2 mux1 mux0 page 72 $06 ($26) adcsr aden adsc adfr adif adie adps2 adps1 adps0 page 72 $05 ($25) adch - - - - - - adc9 adc8 page 73 $04 ($24) adcl adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 page 73 $03 ($20) reserved $02 ($22) reserved $01 ($21) reserved $00 ($20) reserved 119 at90s/ls8535 1041h 11/01 notes: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory address es should never be written. 2. some of the status flags are cleared by writing a logical 1 to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions wo rk with registers $00 to $1f only. 120 at90s/ls8535 1041h 11/01 instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl, k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl, k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd = rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? = kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd = rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one s complement rd $ff ? rd z,c,n,v 1 neg rd two s complement rd $00 ? rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc = pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc = pc + 2 or 3 none 1/2/3 cp rd, rr compare rd ? rr z,n,v,c,h 1 cpc rd, rr compare with carry rd ? rr ? c z,n,v,c,h 1 cpi rd, k compare register with immediate rd ? k z,n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b) = 1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc = pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc = pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 data transfer instructions mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, -x load indirect and pre-dec. x x - 1, rd (x) none 2 121 at90s/ls8535 1041h 11/01 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, -y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd, y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z + 1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) = rr none 2 st x+, rr store indirect and post-inc. (x) = rr, x x + 1 none 2 st -x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st -y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q, rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q, rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 in rd, p in port rd p none 1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1 none 2 cbi p, b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) = c, rd(n+1) rd(n), c = rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) = c, rd(n) rd(n+1), c = rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i = 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two s complement overflow v 1v1 clv clear two s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) mnemonic operands description operation flags # clocks 122 at90s/ls8535 1041h 11/01 ordering information power supply speed (mhz) ordering code package operation range 2.7 - 6.0v 4 at90ls8535-4ac at90ls8535-4jc at90ls8535-4pc at90ls8535-4mc 44a 44j 40p6 44m1 commercial (0 c to 70 c) at90ls8535-4ai at90ls8535-4ji at90ls8535-4pi at90ls8535-4mi 44a 44j 40p6 44m1 industrial (-40 c to 85 c) 4.0 - 6.0v 8 at90s8535-8ac at90s8535-8jc AT90S8535-8PC at90ls8535-8mc 44a 44j 40p6 44m1 commercial (0 c to 70 c) at90s8535-8ai at90s8535-8ji at90s8535-8pi at90ls8535-8mi 44a 44j 40p6 44m1 industrial (-40 c to 85 c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 40p6 40-lead, 0.600" wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf) 123 at90s/ls8535 1041h 11/01 packaging information 44a 1.20(0.047) max 10.10(0.394) 9.90(0.386) sq 12.25(0.482) 11.75(0.462) sq 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) 0.20(0.008) 0.09(0.004) 0 ? ~7 ? 0.80(0.0315) bsc pin 1 id 0.45(0.018) 0.30(0.012) pin 1 *controlling dimension: millimetter 44-lead, thin (1.0mm) plastic quad flat package (tqfp), 10x10mm body, 2.0mm footprint, 0.8mm pitch. dimension in millimeters and (inches)* jedec standard ms-026 acb rev. a 04/11/2001 124 at90s/ls8535 1041h 11/01 44j 1.14(0.045) x 45? pin no. 1 identify 0.813(0.032) 0.660(0.026) 1.27(0.050) typ 12.70(0.500) ref sq 1.14(0.045) x 45? 0.51(0.020)max 45? max (3x) 0.318(0.0125) 0.191(0.0075) 0.533(0.021) 0.330(0.013) 0.50(0.020)min 3.05(0.120) 2.29(0.090) 4.57(0.180) 4.19(0.165) 16.70(0.656) 16.50(0.650) 17.70(0.695) 17.40(0.685) sq sq 2.11(0.083) 1.57(0.062) 16.00(0.630) 15.00(0.590) sq 44j, 44-lead, plastic j-leaded chip carrier (plcc) dimensions in milimeters and (inches)* jedec standard ms-018 ac *controlling dimensions: inches rev. a 04/11/2001 125 at90s/ls8535 1041h 11/01 40p6 52.71(2.075) 51.94(2.045) pin 1 13.97(0.550) 13.46(0.530) 0.38(0.015)min 0.56(0.022) 0.38(0.015) ref 15.88(0.625) 15.24(0.600) 1.65(0.065) 1.27(0.050) 17.78(0.700)max 0.38(0.015) 0.20(0.008) 2.54(0.100)bsc 3.56(0.140) 3.05(0.120) seating plane 4.83(0.190)max 48.26(1.900) ref 0 ~ 15 40-lead, plastic dual inline parkage (pdip), 0.600" wide demension in millimeters and (inches)* jedec standard ms-011 ac *controlling dimension: inches rev. a 04/11/2001 126 at90s/ls8535 1041h 11/01 44m1 2325 orchard parkway san jose, ca 95131 title 44m1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mm micro lead frame package (mlf) drawing no. rev a r 07/23/01 44m1 e d2 e2 l e b a a1 seating plane top view bottom view side view marked pin#1 identifier pin #1 corner (*unit of measure = mm) common dimensions a3 symbol min nom max note e2 2.25 4.70 5.25 d2 l 0.35 0.55 0.75 b a 2.25 4.70 5.25 0.80 0.90 1.00 0.00 0.02 0.05 0.18 0.23 0.30 0.25 ref 7.00 bsc d a1 e 7.00 bsc e 0.50 bsc a3 note 1. jedec standard mo-220, fig 1 (saw singulation), vkkd-1 d ? atmel corporation 2001. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company s standard warranty which is detailed in atmel s terms and conditions located on the company s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel product operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-7658-3000 fax (33) 4-7658-3480 atmel heilbronn theresienstrasse 2 pob 3535 d-74025 heilbronn, germany tel (49) 71 31 67 25 94 fax (49) 71 31 67 24 23 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 0 2 40 18 18 18 fax (33) 0 2 40 18 19 60 atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-4253-6000 fax (33) 4-4253-6001 atmel smart card ics scottish enterprise technology park east kilbride, scotland g75 0qr tel (44) 1355-357-000 fax (44) 1355-242-743 e-mail literature@atmel.com web site http://www.atmel.com printed on recycled paper. at m e l and avr are the registered trademarks of atmel. other terms and product names may be the trademarks of others. 1041h 11/01/0m |
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